Abstract: A resistive memory device configurable to operate in either a volatile or a non-volatile memory modes. The device includes top and bottom electrodes with a lithium imbued TiOx switching layer in between, and in the volatile mode can have LRS or HRS states. The decay time scale is electrically and physically tunable. Electroforming permanently configures the volatile device into non-volatile mode. In the non-volatile memory mode, a state-aware write verify (SAW) algorithm based on the logarithmic time dependence of RESET is used, which provides a feedback mechanism to tune the time duration of write pulse during multi-level programming. The time duration is dependent on the read current difference between current resistance state and target resistance state, therefore, the desired time duration of write pulse for specific target resistance states can be deterministically calculated (read current difference is measured with verify operation). This eliminates the number of intermediate-verify steps needed.

Abstract: The disclosure is directed at energy and/or power recycling techniques for use with portable displays in order to extend battery life for portable displays.

Abstract: Low-power electronic components are disclosed, fabricated using a single type of unipolar thin-film transistor (uTFT), such as n-type or p-type devices. The components include logic structures such as static random-access memory (SRAM), data flip-flops (DFFs), and latches, and are particularly suited for use in flexible or display-integrated electronics. Each logic structure comprises a logic core coupled to external power, ground, and optionally control signal lines via two or more fabrics of uTFT-based switching elements. The arrangement avoids direct-current conduction paths between VDD and VSS, or other external lines such as word lines or bit lines. The result is a class of uTFT logic circuits with reduced static power consumption, even in the absence of complementary transistor types. Applications include system-on-panel designs, flexible displays, wearable sensors, and ultra-low-power IoT devices.

Abstract: The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

Abstract: The disclosure is directed at systems and methods for reducing power consumption of electronic displays with in-pixel SRAM or DRAM cell and unweighted pulse width modulation (PWM) scheme.

Abstract: Methods and systems for reducing power consumption in an electronic component. The disclosure uses column line segmentation to reduce the power consumption by segmenting the column lines within the electronic component.

Abstract: Energy and/or power recycling techniques for use with portable displays in order to extend battery life for portable displays.

Abstract: The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

Abstract: A system and method to increase the yield of manufactured integrated circuits by providing remedial circuit elements including alternate plane transistors, manufactured by middle of line and/or back end of line processes, to enable and disable the remedial circuit elements which provide additional circuit functions, when needed, as determined by post-manufacture testing of the integrated circuits and/or by in-operation monitoring of circuit operation. The system and method can address the distribution of the power supply and signals, such as clock signals, and/or high speed I/O signals, through problem areas resulting from sub-optimal designs, circuit aging and/or failures due to manufacturing process variations.

Abstract: The disclosure is directed at a CMOS-like logic gate including a set of thin-film transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.

Abstract: The disclosure is directed at energy and/or power recycling techniques for use with portable displays in order to extend battery life for portable displays.

Abstract: Physically unclonable functions response in memory cells is improved by transistor sizing, transistor threshold voltage (VT) and body bias in the memory cell to improve the reproducibility of the memory cell and multiple Sense Amplifiers (SA) per column to further enhance physically unclonable function entropy. A physically unclonable function exploits a large number of read-sequence-order combinations available in a physically unclonable function memory array to generate an exponentially large challenge-response pair space, without incurring the area and energy costs of hosting and operating an exponentially large memory array.

Abstract: An electronic circuit for thin-film transistors, the circuit including: a driving TFT; an input signal; a compensation TFT provided between gate and source terminals of the driving TFT; a storage TFT provided between the input signal and the gate of the driving TFT; a plurality of switching TFTs configured to charge the storage TFT from the input signal in one cycle and then charge the compensation TFT from the storage TFT during another cycle, such that the compensation TFT compensates for degradation of the driving TFT. An opto-electronic fabrication method including: forming an opto-electronic device on a growth substrate; temporarily bonding the opto-electronic device to a carrier substrate; removal of the growth substrate; etching the opto-electronic device to a predetermined height; coating the opto-electronic device with a functional metal layer; bonding the opto-electronic device onto a final receiver substrate; and removing the carrier substrate.

Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.

Abstract: Physically unclonable functions response in memory cells is improved by transistor sizing, transistor threshold voltage (VT) and body bias in the memory cell to improve the reproducibility of the memory cell and multiple Sense Amplifiers (SA) per column to further enhance physically unclonable function entropy. A physically unclonable function exploits a large number of read-sequence-order combinations available in a physically unclonable function memory array to generate an exponentially large challenge-response pair space, without incurring the area and energy costs of hosting and operating an exponentially large memory array.

Abstract: A unipolar inverter circuit for thin-film transistor circuits including: a driving voltage input; an input signal; a base voltage input; a first stage having a first inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal; a capacitor coupled to the output of the first stage at a node A; and a second stage having: a second inverter circuit having a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B; and a clamping transistor connected between the driving voltage and the node B for controlling a voltage, wherein the clamping transistor gate is connected to the driving voltage input; and an output, wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing at the output based on the input signal.

Abstract: An embodiment of a semiconductor package apparatus may include technology to generate a first output from a physically unclonable function (PUF) based on a challenge, modify the challenge based on the first output, and generate a response based on the modified challenge. Some embodiments may additionally or alternatively include technology to change a read sequence of the PUF based on an output of the PUF. Some embodiments may additionally or alternatively include technology to vary a latency of a linear feedback shift register based on an output from the PUF. Other embodiments are disclosed and claimed.

Abstract: A unipolar inverter circuit for thin-film transistor circuits including: a driving voltage input; an input signal; a base voltage input; a first stage having a first inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal; a capacitor coupled to the output of the first stage at a node A; and a second stage having: a second inverter circuit having a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B; and a clamping transistor connected between the driving voltage and the node B for controlling a voltage, wherein the clamping transistor gate is connected to the driving voltage input; and an output, wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing at the output based on the input signal.

Abstract: Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.

Abstract: A storage cell is provided with improved robustness to soft errors. The storage cell comprises complementary core storage nodes and complementary outer storage nodes. The outer storage nodes act to limit feedback between the core storage nodes and are capable of restoring the logical state of the core storage nodes in the event of a soft error. Similarly the core storage nodes act to limit feedback between the outer storage nodes with the same effect. This cell has advantages compared with other robust storage cells in that there are only two paths between the supply voltage and ground which limits the leakage power. An SRAM cell utilizing the proposed storage cell can be realized with two access transistors configured to selectively couple complementary storage nodes to a corresponding bitline. A flip-flop can be realized with a variety of transfer gates which selectively couple data into the proposed storage cell.