Abstract: A method and apparatus for testing a static random access memory (SRAM) array for the presence of weak defects. A 0/1 ratio is first written to the memory array (step 100), following which the bit lines BL and BLB are pre-charged and equalized to a threshold detection voltage (step 102). The threshold detection voltage is programmed according to the 0/1 ratio of cells, so as to take into account specific cell criterion and/or characteristics. Next, the word lines associated with all of the cells in the array are enabled substantially simultaneously (step 104), the bit lines are then shorted together (step 106), the word lines are disabled (step 108) and the bit lines are released (step 110). Following these steps, the contents of the SRAM array are read and compared against the original 0/1 ratio (step 112). 10 Any cells whose contents do not match the original 0/1 ratio (i.e. those whose contents have flipped) are marked or otherwise identified as “weak” (step 114).

Abstract: An adjustable PTAT provides a load current comprising at least a first and second current. The load current has a desired temperature coefficient and the PTAT comprises at least two transistor groups. The first transistor group provides the first current having a negative temperature coefficient. Modification to the first transistor group results in a change in the temperature coefficient without affecting the value of the first current. The second transistor group provides the second current having a positive temperature coefficient, wherein modification to the second transistor group results in a change in the temperature coefficient without affecting the value of the second current. The temperature coefficient of the load current is determined by adjusting the temperature coefficient of one or both of the first and second transistor groups.

Abstract: A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.

Abstract: A technique is described to allow testing of high-speed digital circuits using lower speed testing equipment, to circuits to be placed into a sleep mode, and to allow burn-in testing of digital circuits with minimal overhead in terms of silicon area or performance.

Abstract: A flipflop has master and slave interconnected through a buffer. The master has its inverters located outside the signal path from input to output, as the buffer provides the driving capability required for both IDDQ-testing and operational use. This configuration enables IDDQ-testing without further circuitry added to the flipflop and reduces propagation delay in the signal path.

Abstract: A circuit including a data signal input to receive a data signal, a clock signal input to receive a clock signal, a clocking circuit to generate control clocks, and a multiple input conditional inverter to receive the data signal and control clocks, and to generate an output. The circuit also includes at least one stack node pre-charging transistor coupled to a high signal transfer node in the multiple input conditional inverter and at least one stack node pre-discharging transistor coupled to a low signal transfer node in the multiple input conditional inverter. A keeper circuit receives the output of the multiple input conditional inverter and a buffer circuit receives the output of the multiple input conditional inverter and generates the circuit output.

Abstract: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Abstract: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Abstract: A flip-flop circuit uses a multiple input conditional inverter activated by clock signals to transfer a sample of the input data to a keeper circuit. The keeper circuit signal is buffered to provide the flip-flop circuit output.

Abstract: An electronic device, with a plurality of logic stages for functional collaboration, is provided with selection means for selectively operating the plurality of stages to form either a sequential logic circuit or a combinatorial logic circuit. This enables conversion of sequential logic circuitry into combinatorial logic circuitry for the purpose of effective I.sub.DDQ -testing.

Abstract: The invention relates to an integrated circuit comprising a dynamic CMOS Programmable Logic Array (PLA) with an AND plane and an OR plane. The invention also relates to a method for testing such a circuit. A PLA according to the invention is provided with means enabling detection of bridging faults. Adjacent lines can be driven to complementary logic levels. Crosspoint transistors can be switched off. In this way, bridging faults between lines give rise to an observable elevated quiescent power supply current (IDDQ).

Abstract: The invention relates to an integrated circuit, containing an A/D converter and a test circuit, the latter in a test mode enabling explicit testing of analog and digital control signals of the circuit by supplying these control signals to circuit sections of the A/D converter and thus generating digital data signals at the output of the A/D converter. Analog signals, like bias signals and reference signals, can be selected and supplied to the input facility of the converter. Subsequently, a digital representation of the selected signal is obtained at the output facility of the converter. Digital signals, like clock signals, can be selected and supplied directly to the output facility. The output facility is operated by a clock signal and constructs a clocked version of the selected digital signal, which is subsequently available at the output. Thus, selected signals, either digital or analog, are available at the output of the converter and can be compared to specified data.

Abstract: Hard-open defects between logic gates of an address decoder and the voltage supply render a memory conditionally inoperative. The decoders are therefore examined for such hard-open defects. Two cells of two logically adjacent rows or columns are written with complementary logic data. If a Read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect in the decoders is demonstrated. Alternatively, the memory is provided with a fault-tolerant decoder that comprises additional disabling circuitry to properly disable the rows and columns even when a hard-open defect is present in the decoders' logic gates.

Abstract: A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.

Abstract: An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault.

Abstract: A bias generator is tested in an I.sub.DDQ -scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.

Abstract: An IC is tested through I.sub.DDQ -measurements. The IC's substrate includes a region of a conductivity type with a supply node for supply of the circuit and with a biasing node for connection to a biasing voltage to bias the region. I.sub.DDQ -testing of the circuit is conducted while the supply node and the biasing node are galvanically disconnected to separate the contribution to the quiescent current from the circuit functionality features from the contribution to the quiescent current from the biasing features.

Abstract: An SRAM has a plurality of respective memory cells coupled to a respective one of a plurality of word lines and to a pair of bit lines. The SRAM comprises I.sub.DDQ test means to render the word lines active in parallel by cumulatively increasing a number of active ones among the word lines. This permits the writing of a specific logic state in all cells of a column through the tiny bit line drivers that are progressively assisted by the cells already written, thus avoiding the use of additional heavy write circuitry for I.sub.DDQ test purposes only.

Abstract: An electronic circuit includes an array of a number of memory cells that are functionally organized in rows and columns. The circuit includes test circuitry that is selectively operative to access all cells of the array in parallel. An I.sub.DDQ -test then discovers whether or not there is a defect in any of the cells. This results in a test circuit which is faster, more efficient and more economical than previously-available circuits.