Patents by Inventor Manoj Sastry

Manoj Sastry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12120227
    Abstract: A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.
    Type: Grant
    Filed: October 25, 2022
    Date of Patent: October 15, 2024
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Marcio Juliato, Manoj Sastry
  • Patent number: 12120212
    Abstract: Time recovery techniques are described. A method comprises receiving messages from the first device by the second device in the first network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time, determining the second clock is to recover the network time for the second device without new messages from the first device, retrieving a first set of timestamps previously stored for events in the first network domain using the network time from the second clock, retrieving a second set of timestamps previously stored for the events in the first network domain using a redundant time from a third clock, where the third clock is not synchronized with the first and second clocks, and recovering the network time using a regression model and the redundant time from the third clock.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: October 15, 2024
    Assignee: INTEL CORPORATION
    Inventors: Vuk Lesi, Christopher Gutierrez, Manoj Sastry, Christopher Hall, Marcio Juliato, Shabbir Ahmed, Qian Wang
  • Patent number: 12111908
    Abstract: Systems, apparatuses, and methods to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. ECUs transmit messages by manipulating voltage on conductive lines of the bus. Observation circuitry can observe voltage signals associated with the transmission at a point on the in-vehicle network bus. A distribution can be generated from densities of the voltage signals. ECUs can be identified and/or fingerprinted based on the distributions.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: October 8, 2024
    Assignee: INTEL CORPORATION
    Inventors: Eduardo Alban, Shabbir Ahmed, Marcio Juliato, Christopher Gutierrez, Qian Wang, Vuk Lesi, Manoj Sastry
  • Patent number: 12095782
    Abstract: Techniques to secure a time sensitive network are described. An apparatus may establish a data stream between a first device and a second device in a network domain, the network domain includes a plurality of switching nodes, receive messages from the first device by the second device in the network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time for the network domain, update a correction field for a received message with a residence time and time delay value by the second device, determine whether the updated message is benign or malicious, update the correction field for the updated message with an inference time when the updated message is benign, and prevent relay of the updated message to other devices in the network domain when the updated message is malicious.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: September 17, 2024
    Assignee: INTEL CORPORATION
    Inventors: Christopher Gutierrez, Vuk Lesi, Manoj Sastry, Christopher Hall, Marcio Juliato, Shabbir Ahmed, Qian Wang
  • Patent number: 12086596
    Abstract: Techniques are described for an instruction for a conditional rotate and XOR operation in a single instruction and triple input bitwise logical operations in a single instruction in an instruction set of a computing system.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: September 10, 2024
    Assignee: Intel Corporation
    Inventors: Christoph Dobraunig, Santosh Ghosh, Manoj Sastry
  • Patent number: 12081561
    Abstract: Systems and methods to detect attacks on the clocks of devices. In time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on key performance indicators related to the protecting transmission windows in data streams of the time sensitive networks.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: September 3, 2024
    Assignee: INTEL CORPORATION
    Inventors: Javier Perez-Ramirez, Mikhail Galeev, Marcio Juliato, Christopher Gutierrez, Dave Cavalcanti, Manoj Sastry, Kevin Stanton, Vuk Lesi
  • Publication number: 20240267212
    Abstract: Key encapsulation implemented by random sample generator circuitry to generate a plurality of pseudorandom bitstreams; polynomial multiplier circuitry to multiply a plurality of polynomial coefficients; and a controller to power off the polynomial multiplier circuitry and power on the random sample generator circuitry to generate the plurality of pseudorandom bitstreams, and power off the random sample generator circuitry and power on the polynomial multiplier circuitry to multiple the plurality of polynomial coefficients.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Manoj Sastry
  • Publication number: 20240264837
    Abstract: Techniques are described for an instruction for a conditional rotate and XOR operation in a single instruction and triple input bitwise logical operations in a single instruction in an instruction set of a computing system.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 8, 2024
    Applicant: Intel Corporation
    Inventors: Christoph Dobraunig, Santosh Ghosh, Manoj Sastry
  • Publication number: 20240267390
    Abstract: Techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. Embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. Embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. Other embodiments are described and claimed.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Applicant: INTEL CORPORATION
    Inventors: Marcio Juliato, Javier Perez-Ramirez, Manoj Sastry, Dave Cavalcanti, Christopher Gutierrez, Vuk Lesi, Shabbir Ahmed
  • Patent number: 12058261
    Abstract: An apparatus comprises an input register comprising an input polynomial, a processing datapath communicatively coupled to the input register comprising a plurality of compute nodes to perform a number theoretic transform (NTT) algorithm on the input polynomial to generate an output polynomial in NTT format. The plurality of compute nodes comprises at least a first butterfly circuit to perform a series of butterfly calculations on input data and a randomizing circuitry to randomize an order of the series of butterfly calculations.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: August 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Andrea Basso, Dumitru-Daniel Dinu, Avinash L. Varna, Manoj Sastry
  • Patent number: 12054119
    Abstract: Systems, apparatuses, and methods to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. ECUs transmit messages by manipulating voltage on conductive lines of the bus. Observation circuitry can observe voltage transitions associated with the transmission at a point on the in-vehicle network bus. A domain bitmap can be generated from the observed voltage transitions. ECUs can be identified and/or fingerprinted based on the domain bitmaps.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Shabbir Ahmed, Marcio Juliato, Christopher Gutierrez, Qian Wang, Vuk Lesi, Manoj Sastry
  • Patent number: 12055655
    Abstract: Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals is provided. In particular, the disclosure provides an intrusion detection system adapted to receive radar signals and distinguish a potential ghost target from a legitimate target based on a signal to noise ratio of the radar signals and a range to the ghost target and the legitimate target.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Qian Wang, Shabbir Ahmed, Christopher Gutierrez, Wen-Ling Huang, Marcio Juliato, Saiveena Kesaraju, Vuk Lesi, Manoj Sastry, Ivan Simoes Gaspar
  • Patent number: 12047398
    Abstract: Techniques and screening messages based on tags in an automotive environment, such as, messages communicated via a communication bus, like the CAN bus. Messages can be tagged with either a binary or probabilistic tag indicating whether the message is fraudulent. ECUs coupled to the CAN bus can receive the messages and the message tags and can determine whether to fully consume the message based on the tag.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: July 23, 2024
    Assignee: INTEL CORPORATION
    Inventors: Marcio Juliato, Manoj Sastry, Michael Kara-Ivanov, Aviad Kipnis, Shabbir Ahmed, Christopher Gutierrez, Vuk Lesi
  • Patent number: 12047514
    Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Manoj Sastry, Prakash Iyer, Ting Lu
  • Patent number: 12045348
    Abstract: Logic may implement observation layer intrusion detection systems (IDSs) to combine observations by intrusion detectors and/or other intrusion detection systems. Logic may monitor one or more control units at one or more observation layers of an in-vehicle network, each of the one or more control units to perform a vehicle function. Logic may combine observations of the one or more control units at the one or more observation layers. Logic may determine, based on a combination of the observations, that one or more of the observations represent an intrusion. Logic may determine, based at least on the observations, characteristics of an attack, and to pass the characteristics of the attack information to a forensic logging system to log the attack or pass the characteristics of the attack to a recovery system for informed selection of recovery procedures. Logic may dynamically adjust a threshold for detection of suspicious activity.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: July 23, 2024
    Assignee: INTEL CORPORATION
    Inventors: Christopher N. Gutierrez, Marcio Juliato, Shabbir Ahmed, Qian Wang, Manoj Sastry, Liuyang L Yang, Xiruo Liu
  • Patent number: 12034736
    Abstract: Systems and methods to detect attacks on the clocks of devices in time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on pseudo-random numbers generated and used to select and authenticate timing of transmission of messages in protected transmission windows.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: July 9, 2024
    Assignee: INTEL CORPORATION
    Inventors: Marcio Juliato, Javier Perez-Ramirez, Mikhail Galeev, Christopher Gutierrez, Dave Cavalcanti, Manoj Sastry, Vuk Lesi
  • Publication number: 20240223603
    Abstract: Techniques include receiving a message with time information from a clock leader by a clock follower in a time-synchronized network (TSN), the time information to synchronize a clock to a network time for the TSN, retrieving an actual time offset value for the message, the actual time offset value to comprise a value between an actual sending time and an actual receiving time of the message, retrieving an estimated time offset value for the message, the estimated time offset value to comprise a value between an estimated sending time and an estimated receiving time of the message, the estimated time offset value generated using a physics-aware model of the TSN and a clock adjustment value for the clock based on the time information, and determining whether the time information for the message was modified to cause the clock to desynchronize based on difference information. Other embodiments are described and claimed.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Vuk Lesi, Christopher Gutierrez, Shabbir Ahmed, Marcio Juliato, Manoj Sastry
  • Publication number: 20240223585
    Abstract: Techniques include receiving a message with time information at an ingress queue for an ingress interface of an intrusion detection system (IDS), the IDS to monitor a network node of a time-synchronized network (TSN), generating an entrance timestamp for the message, the entrance timestamp to comprise a time value representing when the message is received at the ingress queue of the ingress interface of the IDS, inspecting the message for indications of a security attack by the IDS, generating an exit timestamp for the message, the exit timestamp to comprise a time value representing when the message is received at an egress queue of an egress interface of the IDS, and generating an inspection time interval associated with the IDS, the inspection time interval to represent a time interval between the entrance timestamp and the exit timestamp for the message while transiting the IDS. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Christopher Gutierrez, Vuk Lesi, Marcio Juliato, Manoj Sastry, Shabbir Ahmed
  • Patent number: 12026516
    Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rot
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: July 2, 2024
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
  • Publication number: 20240211261
    Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rot
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry