Patents by Inventor Manoj Sastry
Manoj Sastry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240211261Abstract: A method comprises fetching, by fetch circuitry, an encoded XOR3P instruction comprising at least one opcode, a first source identifier to identify a first register, a second source identifier to identify a second register, a third source identifier to identifier a third register, and a fourth source identifier to identify a fourth operand, wherein the first register is to store a first value, the second register is to store a second value, and the third register is to store a third value, decoding, by decode circuitry, the encoded XOR3P instruction to generate a decoded XOR3P instruction, and executing, by execution circuitry, to execute the decoded XOR3P instruction to perform a rotate operation on the third value based on the fourth operand to generate a rotated third value, perform an XOR operation on the first value, the second value, and the rotated third value to generate an XOR result, perform a rotate operation on the XOR result based on the fourth operand to generate a rotated XOR, and store the rotType: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry
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Publication number: 20240211253Abstract: A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.Type: ApplicationFiled: December 22, 2022Publication date: June 27, 2024Applicant: Intel CorporationInventors: Santosh Ghosh, Christoph Dobraunig, Manoj Sastry, Andrew H. Reinders, Regev Shemy, Qian Wang, Rotem Ohana Peretz, Wing Shek Wong, Wajdi Feghali
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Patent number: 12000957Abstract: Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals and ranges determined from the radar signals. In particular, the disclosure provides an intrusion detection system receiving ranges and velocities for targets detected based on radar signals, determining a potential ghost target from the received velocities and confirming the potential ghost target based on estimated ranges and perturbations of the vehicle speed.Type: GrantFiled: June 24, 2021Date of Patent: June 4, 2024Assignee: INTEL CORPORATIONInventors: Vuk Lesi, Shabbir Ahmed, Christopher Gutierrez, Wen-Ling Huang, Marcio Juliato, Saiveena Kesaraju, Manoj Sastry, Ivan Simoes Gaspar, Qian Wang
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Patent number: 11995183Abstract: Systems, apparatuses, and methods to response to detected attacks in an autonomous system based on context of the autonomous system are described. In particular, the disclosure provides an intrusion detection system receiving contexts and contracts dictating particular response guide rails from a higher level components or stack on the autonomous system. The intrusion detection system is arranged to respond to attacks according to the contract without intervention by the higher level components or stack.Type: GrantFiled: June 24, 2021Date of Patent: May 28, 2024Assignee: INTEL CORPORATIONInventors: Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez, Vuk Lesi, Manoj Sastry, Qian Wang
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Patent number: 11995184Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.Type: GrantFiled: September 24, 2021Date of Patent: May 28, 2024Assignee: INTEL CORPORATIONInventors: Santosh Ghosh, Andrea Basso, Manoj Sastry
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Publication number: 20240171593Abstract: Techniques include an apparatus to retrieve a first parameter for the IDS to monitor a device for a time-synchronized network. The first parameter may represent a number of messages the IDS needs to analyze in order to detect a security attack. The messages may comprise time information to synchronize a clock for a device to a network time for a time-synchronized network. The processor circuitry may retrieve a second parameter for a time sensitive application. The second parameter may represent a defined amount of time error tolerated by the time sensitive application, and determine a third parameter for the IDS based on the first and second parameters. The third parameter may represent a defined frequency to receive a number of messages with time information in order to detect the security attack on the device within a defined time interval. Other embodiments are described and claimed.Type: ApplicationFiled: November 18, 2022Publication date: May 23, 2024Applicant: Intel CorporationInventors: Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez, Vuk Lesi, Manoj Sastry
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Patent number: 11985226Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a ? step of a SHA calculation, a second section to perform a ? step and a ? step of the SHA calculation, a third section to perform a ? step of the SHA calculation and a fourth section to perform a ? step of the SHA calculation.Type: GrantFiled: December 23, 2020Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Marcio Juliato, Manoj Sastry
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Publication number: 20240143020Abstract: An apparatus for clock manager redundancy comprises a clock circuitry to manage a clock for a device; a first processing circuitry coupled to the clock circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; a hardened execution environment coupled to the clock circuitry and the first processing circuitry, the hardened execution environment to comprise: a detector to monitor the clock manager and generate an alert when the detector identifies abnormal behavior of the clock manager; and a second processing circuitry to execute instructions to perform operations for a redundant clock manager, the redundant clock manager to take over operations for the clock manager in response to the alert from the detector. Other embodiments are described and claimed.Type: ApplicationFiled: October 26, 2022Publication date: May 2, 2024Applicant: Intel CorporationInventors: Vuk Lesi, Christopher Gutierrez, Shabbir Ahmed, Marcio Juliato, Manoj Sastry
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Patent number: 11966503Abstract: Systems, apparatuses, and methods to mitigate effects of glitch attacks on a broadcast communication bus are provided. The voltage levels of the communication bus are repeatedly sampled to identify glitch attacks. The voltage level on the communication bus can be overdriven or overwritten to either corrupt received messages or correct received messages.Type: GrantFiled: September 24, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Marcio Juliato, Vuk Lesi, Christopher Gutierrez, Shabbir Ahmed, Qian Wang, Manoj Sastry
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Patent number: 11949793Abstract: Various embodiments are generally directed to providing authentication and confidentiality mechanisms for message communication over an in-vehicle network. For example, authentication data associated with a communicating node may be transmitted over the network by encoding different predefined voltage levels on top of the message bits of the message being communicated. Different voltage levels may represent different encodings, such as a bit-pair or any bit combination of the authentication data. In a further example, messaging confidentiality between at least two communicating nodes may be achieved by pseudo-randomly flipping, or scrambling, the dominant and recessive voltages of the entire message frame at the analog level based on a pseudo-random control bit sequence.Type: GrantFiled: July 19, 2022Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez, Xiruo Liu, Manoj Sastry, Liuyang Yang
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Patent number: 11930365Abstract: Systems, apparatus, methods, and techniques for reporting an attack or intrusion into an in-vehicle network are provided. The attack can be broadcast to connected vehicles over a vehicle-to-vehicle network. The broadcast can include an indication of a sub-system involved in the attack and can include a request for assistance in recovering from the attack. Connected vehicles can broadcast responses over the vehicle-to-vehicle network. The responses can include indications of data related to the compromised sub-system. The vehicle can receive the responses and can use the responses to recover from the attack, such as, estimate data.Type: GrantFiled: May 12, 2022Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Liuyang Yang, Xiruo Liu, Manoj Sastry, Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez
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Patent number: 11917053Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.Type: GrantFiled: March 29, 2022Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
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Patent number: 11904872Abstract: Systems, apparatus, methods, and techniques for an ego vehicle to respond to detecting misbehaving information from remote vehicles are provided. An ego vehicle, in addition to reporting misbehaving vehicles to a misbehavior authority via a vehicle-to-anything communication network, can, take additional actions based in part on how confident the ego vehicle is about the evidence of misbehavior. Where the confidence is high the ego vehicle can simply discard the misbehaving data and provide an alternative estimate for such data from alternative sources. Where the confidence is not high the ego vehicle can request assistance from neighboring vehicles and roadside units to provide independent estimates of the data to increase confidence in the evidence of misbehavior.Type: GrantFiled: July 6, 2022Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Xiruo Liu, Liuyang Yang, Manoj Sastry, Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez
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Patent number: 11909857Abstract: Systems, apparatus, methods, and techniques for functional safe execution of encryption operations are provided. A fault tolerant counter and a complementary pair of encryption flows are provided. The fault tolerant counter may be based on a gray code counter and a hamming distance checker. The complementary pair of encryption flows have different implementations. The output from the complementary pair of encryption flows can be compared, and where different, errors generated.Type: GrantFiled: December 23, 2019Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Santosh Ghosh, Marcio Juliato, Rafael Misoczki, Manoj Sastry, Liuyang Yang, Shabbir Ahmed, Christopher Gutierrez, Xiruo Liu
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Patent number: 11902297Abstract: Systems, apparatuses, and methods to establish a mapping between message identifications for messages transmitted on a communication bus and electronic control units transmitting the messages is provided. In particular, retransmission of a low priority message onto the bus is forced such that the retransmitted low priority message overlaps with a higher priority message to determine whether the messages originated from the same ECU.Type: GrantFiled: March 26, 2021Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Christopher Gutierrez, Shabbir Ahmed, Marcio Juliato, Vuk Lesi, Manoj Sastry, Qian Wang
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Patent number: 11889300Abstract: Various embodiments are generally directed to techniques for providing improved privacy protection against vehicle tracking for connected vehicles of a vehicular network. For example, at least one road side unit may: identify a set of vehicles that require pseudonym changes and send an invitation for a pseudonym change event to each of the vehicles, determine at least a total number of the acceptances, determine whether the total number meets or exceeds a predetermined threshold number, send acknowledgement messages to the accepting vehicles if the threshold number is met, and form a vehicle group to coordinate the pseudonym change event during a privacy period. During the privacy period, the RSU and the vehicles may communicate with each other in a confidential and private manner via key-session-based unicast transmission, and coordinate transmission power and vehicle trajectory adjustments to maximize the benefits for safety and obfuscation for privacy.Type: GrantFiled: December 10, 2021Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Xiruo Liu, Shabbir Ahmed, Ralf Graefe, Christopher Gutierrez, Marcio Juliato, Rafael Rosales, Manoj Sastry, Liuyang Yang
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Patent number: 11875235Abstract: Systems, apparatuses, and methods to establish ground truth for an intrusion detection system using machine learning models to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. Voltage signatures for overlapping message identification (MID) numbers are collapsed and trained on a single ECU label.Type: GrantFiled: September 17, 2020Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Shabbir Ahmed, Christopher Gutierrez, Marcio Juliato, Qian Wang, Vuk Lesi, Manoj Sastry
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Patent number: 11847211Abstract: A platform comprising numerous reconfigurable circuit components arranged to operate as primary and redundant circuits is provided. The platform further comprises security circuitry arranged to monitor the primary circuit for anomalies and reconfigurable circuit arranged to disconnect the primary circuit from a bus responsive to detection of an anomaly. Furthermore, the present disclosure provides for the quarantine, refurbishment and designation as redundant, the anomalous circuit.Type: GrantFiled: May 12, 2022Date of Patent: December 19, 2023Assignee: INTEL CORPORATIONInventors: Marcio Juliato, Manoj Sastry, Shabbir Ahmed, Christopher Gutierrez, Qian Wang, Vuk Lesi
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Patent number: 11823022Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.Type: GrantFiled: May 12, 2022Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Marcio Juliato, Christopher Gutierrez, Shabbir Ahmed, Manoj Sastry, Liuyang Yang, Xiruo Liu
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Publication number: 20230342450Abstract: Systems, apparatuses, and methods to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. ECUs transmit messages by manipulating voltage on conductive lines of the bus. Observation circuitry can observe voltage signals associated with the transmission at a point on the in-vehicle network bus. A distribution can be generated from densities of the voltage signals. ECUs can be identified and/or fingerprinted based on the distributions.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Applicant: Intel CorporationInventors: Eduardo Alban, Shabbir Ahmed, Marcio Juliato, Christopher Gutierrez, Qian Wang, Vuk Lesi, Manoj Sastry