Patents by Inventor Manoj Sastry

Manoj Sastry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11424907
    Abstract: Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Andrew H. Reinders, Joseph Friel, Avinash Laxmisha Varna, Manoj Sastry
  • Publication number: 20220255757
    Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 11, 2022
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Manoj Sastry, Prakash Iyer, Ting Lu
  • Patent number: 11407423
    Abstract: Systems, apparatus, methods, and techniques for an ego vehicle to respond to detecting misbehaving information from remote vehicles are provided. An ego vehicle, in addition to reporting misbehaving vehicles to a misbehavior authority via a vehicle-to-anything communication network, can, take additional actions based in part on how confident the ego vehicle is about the evidence of misbehavior. Where the confidence is high the ego vehicle can simply discard the misbehaving data and provide an alternative estimate for such data from alternative sources. Where the confidence is not high the ego vehicle can request assistance from neighboring vehicles and roadside units to provide independent estimates of the data to increase confidence in the evidence of misbehavior.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 9, 2022
    Assignee: INTEL CORPORATION
    Inventors: Xiruo Liu, Liuyang Yang, Manoj Sastry, Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez
  • Patent number: 11409286
    Abstract: Systems, methods, computer program products, and apparatuses for low latency, fully reconfigurable hardware logic for ensemble classification methods, such as random forests. An apparatus may comprise circuitry for an interconnect and circuitry for a random forest implemented in hardware. The random forest comprising a plurality of decision trees connected via the interconnect, each decision tree comprising a plurality of nodes connected via the interconnect. A first decision tree of the plurality of decision trees comprising a first node of the plurality of nodes to: receive a plurality of elements of feature data via the interconnect, select a first element of feature data, of the plurality of elements of feature data, based on a configuration of the first node, and generate an output based on the first element of feature data, an operation, and a reference value, the operation and reference value specified in the configuration of the first node.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 9, 2022
    Assignee: INTEL CORPORATION
    Inventors: Marcio Juliato, Christopher Gutierrez, Shabbir Ahmed, Manoj Sastry, Liuyang Yang, Xiruo Liu
  • Publication number: 20220247561
    Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.
    Type: Application
    Filed: March 21, 2022
    Publication date: August 4, 2022
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Andrew H. Reinders, Manoj Sastry
  • Patent number: 11405176
    Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 2, 2022
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Andrew Reinders, Rafael Misoczki, Rosario Cammarota, Manoj Sastry
  • Patent number: 11405213
    Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 2, 2022
    Assignee: INTEL CORPORATION
    Inventors: Santosh Ghosh, Vikram Suresh, Sanu Mathew, Manoj Sastry, Andrew H. Reinders, Raghavan Kumar, Rafael Misoczki
  • Publication number: 20220224701
    Abstract: Techniques to secure a time sensitive network are described. An apparatus may establish a data stream between a first device and a second device in a network domain, the network domain includes a plurality of switching nodes, receive messages from the first device by the second device in the network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time for the network domain, update a correction field for a received message with a residence time and time delay value by the second device, determine whether the updated message is benign or malicious, update the correction field for the updated message with an inference time when the updated message is benign, and prevent relay of the updated message to other devices in the network domain when the updated message is malicious.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Applicant: Intel Corporation
    Inventors: Christopher Gutierrez, Vuk Lesi, Manoj Sastry, Christopher Hall, Marcio Juliato, Shabbir Ahmed, Qian Wang
  • Publication number: 20220224501
    Abstract: Time recovery techniques are described. A method comprises receiving messages from the first device by the second device in the first network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time, determining the second clock is to recover the network time for the second device without new messages from the first device, retrieving a first set of timestamps previously stored for events in the first network domain using the network time from the second clock, retrieving a second set of timestamps previously stored for the events in the first network domain using a redundant time from a third clock, where the third clock is not synchronized with the first and second clocks, and recovering the network time using a regression model and the redundant time from the third clock.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Applicant: Intel Corporation
    Inventors: Vuk Lesi, Christopher Gutierrez, Manoj Sastry, Christopher Hall, Marcio Juliato, Shabbir Ahmed, Qian Wang
  • Patent number: 11386204
    Abstract: A platform comprising numerous reconfigurable circuit components arranged to operate as primary and redundant circuits is provided. The platform further comprises security circuitry arranged to monitor the primary circuit for anomalies and reconfigurable circuit arranged to disconnect the primary circuit from a bus responsive to detection of an anomaly. Furthermore, the present disclosure provides for the quarantine, refurbishment and designation as redundant, the anomalous circuit.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: July 12, 2022
    Assignee: INTEL CORPORATION
    Inventors: Marcio Juliato, Manoj Sastry, Shabbir Ahmed, Christopher Gutierrez, Qian Wang, Vuk Lesi
  • Patent number: 11388598
    Abstract: Systems, apparatus, methods, and techniques for reporting an attack or intrusion into an in-vehicle network are provided. The attack can be broadcast to connected vehicles over a vehicle-to-vehicle network. The broadcast can include an indication of a sub-system involved in the attack and can include a request for assistance in recovering from the attack. Connected vehicles can broadcast responses over the vehicle-to-vehicle network. The responses can include indications of data related to the compromised sub-system. The vehicle can receive the responses and can use the responses to recover from the attack, such as, estimate data.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 12, 2022
    Assignee: INTEL CORPORATION
    Inventors: Liuyang Yang, Xiruo Liu, Manoj Sastry, Marcio Juliato, Shabbir Ahmed, Christopher Gutierrez
  • Patent number: 11362835
    Abstract: In one example an apparatus comprises a computer readable memory; and a signature module to generate a set of cryptographic keys for attestation of group member devices and a set of leaf nodes in a sub-tree of a Merkle tree corresponding to the set of cryptographic keys, forward the set of leaf nodes to a group manager device, receive, from the group manager device, a subset of intermediate nodes in the Merkle tree, the intermediate nodes being common to all available authentications paths through the Merkel tree for signatures originating in the sub-tree, and determine a cryptographic key that defines an authentication path through the Merkle tree, the authentication path comprising one or more nodes from the set of leaf nodes and one or more nodes from the intermediate nodes received from the group manager device. Other examples may be described.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 14, 2022
    Assignee: INTEL CORPORATION
    Inventors: Manoj Sastry, Rafael Misoczki
  • Patent number: 11354406
    Abstract: Methods and apparatus relating to a physics-based approach for attack detection and/or localization in closed-loop controls for autonomous vehicles are described. In an embodiment, multiple state estimators are used to compute a set of residuals to detect, classify, and/or localize attacks. This allows for determination of an attacker's location and the kind of attack being perpetrated. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 7, 2022
    Assignee: INTEL CORPORATION
    Inventors: Marcio Juliato, Shabbir Ahmed, Manoj Sastry, Liuyang L. Yang, Vuk Lesi, Li Zhao
  • Patent number: 11356251
    Abstract: Systems, apparatus, methods, and techniques for facilitating privacy preserving secure communicating in a platoon of devices, such as, vehicles, roadside units, or the like is provided. A service initiator provisions a ring key-set as well as a public key-pair and distributes the keys to user equipment and service coordinators. During operation, user equipment can query, via a service coordinator, the existence of a platoon, form a platoon, or join a platoon with the ring key-set and the public key-pair. To form a platoon the service coordinator can generate a symmetric key and provide the symmetric key to the user equipment. Subsequently, user equipment can communicate using the symmetric key.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Rafael Misoczki, Dave Cavalcanti, Manoj Sastry
  • Publication number: 20220166771
    Abstract: In one example a prover device comprises one or more processors, a computer-readable memory, and signature logic to store a first cryptographic representation of a first trust relationship between the prover device and a verifier device, the first cryptographic representation based on a pair of asymmetric hash-based multi-time signature keys, receive an attestation request message from the verifier device, the attestation request message comprising attestation data for the verifier device and a hash-based signature generated by the verifier device, and in response to the attestation request message, to verify the attestation data, verify the hash-based signature generated by the verifier device using a public key associated with the verifier device, generate an attestation reply message using a hash-based multi-time private signature key and send the attestation reply message to the verifier device. Other examples may be described.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Applicant: Intel Corporation
    Inventors: Xiruo Liu, Rafael Misoczki, Santosh Ghosh, Manoj Sastry
  • Patent number: 11323268
    Abstract: Embodiments are directed to a digital signature verification engine for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including digital signal processing (DSP) blocks and logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device to operate as a signature verification engine for a bit stream, the signature verification engine including a hybrid multiplication unit, the hybrid multiplication unit combining a set of LEs and a set of the DSPs to multiply operands for signature verification.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Santosh Ghosh, Manoj Sastry, Prakash Iyer, Ting Lu
  • Publication number: 20220131708
    Abstract: In one example an apparatus comprises verification circuitry to receive, in a RSA/ECDSA processor, an input message, compute, in the RSA/ECDSA processor, a hash digest (d) for the message, and provide the hash digest as an input to a XMSS/LMS processor. Other examples may be described.
    Type: Application
    Filed: December 9, 2021
    Publication date: April 28, 2022
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Manoj Sastry, Ki Yoon
  • Publication number: 20220131706
    Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Applicant: Intel Corporation
    Inventors: Rafael Misoczki, Vikram Suresh, Santosh Ghosh, Manoj Sastry, Sanu Mathew, Raghavan Kumar
  • Publication number: 20220123949
    Abstract: In one example an apparatus comprises one or more processors, and signature logic to receive a first plurality of state variables for use in a secure hash signature operation, compute a second plurality of operations from the first plurality of state variables to generate a corresponding second plurality of outputs, receive a signature key to be used in a secure hash operation, divide the signature key into a third plurality of chunks, implement, in a pseudo-random order, a fourth plurality of add operations to add the second plurality of outputs to the third plurality of chunks to update the first plurality of state variables. Other examples may be described.
    Type: Application
    Filed: June 23, 2021
    Publication date: April 21, 2022
    Applicant: Intel Corporation
    Inventors: Santosh Ghosh, Manoj Sastry
  • Publication number: 20220123943
    Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 21, 2022
    Applicant: Intel Corporation
    Inventors: Vikram Suresh, Sanu Mathew, Manoj Sastry, Santosh Ghosh, Raghavan Kumar, Rafael Misoczki