Patents by Inventor Manu Gulati

Manu Gulati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9779468
    Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 3, 2017
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Manu Gulati, Arthur L. Spence, Gurjeet S. Saund, Robert P. Esser
  • Patent number: 9747239
    Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: August 29, 2017
    Assignee: Apple Inc.
    Inventors: Gilbert H. Herbeck, Munetoshi Fukami, Manu Gulati
  • Publication number: 20170213557
    Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Inventors: Manu Gulati, Gilbert H. Herbeck, Alexei E. Kosut, Girault W. Jones, Timothy J. Millet
  • Patent number: 9698797
    Abstract: Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: July 4, 2017
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Suhas Kumar Suvarna Ramesh, Venkata Ramana Malladi, Thomas H. Huang, Rakesh L. Notani, Robert E. Jeter, Kai Lun Hsiung
  • Publication number: 20170177256
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 22, 2017
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. de Cesare, Anand Dalal
  • Publication number: 20170168520
    Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventors: Shu-Yi Yu, Erik P. Machnicki, Gilbert H. Herbeck, Kiran B. Kattel, Manu Gulati
  • Patent number: 9659616
    Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 23, 2017
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Erik P. Machnicki, Gilbert H. Herbeck
  • Patent number: 9653079
    Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: May 16, 2017
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Gilbert H. Herbeck, Alexei E. Kosut, Girault W. Jones, Timothy J. Millet
  • Patent number: 9632137
    Abstract: An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: April 25, 2017
    Assignee: Apple Inc.
    Inventors: James D. Ramsay, Manu Gulati, Mitchell Palmer Lichtenberg, Jr.
  • Patent number: 9619377
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: April 11, 2017
    Assignee: Apple Inc.
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. de Cesare, Anand Dalal
  • Publication number: 20170091026
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Publication number: 20170039672
    Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.
    Type: Application
    Filed: August 3, 2015
    Publication date: February 9, 2017
    Inventors: Timothy J. Millet, Manu Gulati, Arthur L. Spence, Gurjeet S. Saund, Robert P. Esser
  • Patent number: 9549373
    Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 17, 2017
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Gilbert H. Herbeck
  • Patent number: 9529403
    Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Parin Patel, Keith Cox, Derek Iwamoto, Cyril de la Cropte de Chanterac, Christopher J. Young
  • Publication number: 20160328322
    Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
    Type: Application
    Filed: May 6, 2015
    Publication date: November 10, 2016
    Inventors: Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Gurjeet S. Saund, Manu Gulati, Shinye Shiu
  • Publication number: 20160313396
    Abstract: An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.
    Type: Application
    Filed: April 22, 2015
    Publication date: October 27, 2016
    Inventors: James D. Ramsay, Manu Gulati, Mitchell Palmer Lichtenberg, JR.
  • Publication number: 20160240193
    Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Manu Gulati, Gilbert H. Herbeck, Alexei E. Kosut, Girault W. Jones, Timothy J. Millet
  • Patent number: 9378150
    Abstract: Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: June 28, 2016
    Assignee: Apple Inc.
    Inventors: Rohit K. Gupta, Manu Gulati
  • Publication number: 20160116969
    Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Sukalpa Biswas, Shinye Shiu, Cyril de la Cropte de Chanterac, Manu Gulati, Pulkit Desai, Rong Zhang Hu
  • Publication number: 20160091954
    Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Cyril de la Cropte de Chanterac, Manu Gulati, Erik P. Machnicki, Keith Cox, Timothy J. Millet