Patents by Inventor Manu Gulati

Manu Gulati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11620243
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: April 4, 2023
    Assignee: Google LLC
    Inventors: Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao, Benjamin Dodge, Albert Meixner, Allan Douglas Knies, Manu Gulati, Rahul Jagdish Thakur, Jason Rupert Redgrave
  • Publication number: 20230093426
    Abstract: An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster.
    Type: Application
    Filed: February 7, 2022
    Publication date: March 23, 2023
    Inventors: Jonathan MASTERS, Pradeep KANAPATHIPILLAI, Manu GULATI, Nitin MAKHIJA
  • Publication number: 20220413581
    Abstract: This application is directed to power management at a processor system having a plurality of domains. Power samples are collected from the domains and combined to generate a system temperature profile including a temporal sequence of system temperature values. When the system temperature profile satisfies a first criterion, it is determined in real time whether a respective system temperature value of the system temperature profile satisfies a second criterion or a third criterion. In accordance with a determination that the respective system temperature value satisfies the second criterion, a power management engine determines power budgets of the domains on a firmware level and enables operations of the domains according to the power budgets. In accordance with a determination that the respective system temperature value satisfies the third criterion, a subset of domains are selected to apply a respective power throttling action directly on a hardware level.
    Type: Application
    Filed: March 22, 2022
    Publication date: December 29, 2022
    Inventors: Alon NAVEH, Anubhav MISHRA, Manu GULATI
  • Publication number: 20220413582
    Abstract: An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.
    Type: Application
    Filed: March 22, 2022
    Publication date: December 29, 2022
    Inventors: Alon NAVEH, Anubhav MISHRA, Manu GULATI
  • Publication number: 20220066536
    Abstract: Methods, systems, and apparatus, for handling applications in an ambient computing system. One of the methods includes determining, by a low-power processing component, that particular sensor signals have a particular property. In response, a machine learning engine performs an inference pass over a machine learning model using the sensor signals to generate a model output. If the model output of the machine learning engine matches an application-specific condition, one or more of the other processing components are activated to execute an particular application corresponding to the application-specific condition.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Lawrence J. Madar, III, Manu Gulati
  • Publication number: 20220058292
    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
    Type: Application
    Filed: September 8, 2021
    Publication date: February 24, 2022
    Inventors: Manu Gulati, Joseph Sokol, JR., Jeffrey R. Wilcox, Bernard J. Semeria, Michael J. Smith
  • Patent number: 11199896
    Abstract: Methods, systems, and apparatus, for handling applications in an ambient computing system. One of the methods includes determining, by a low-power processing component, that particular sensor signals have a particular property. In response, a machine learning engine performs an inference pass over a machine learning model using the sensor signals to generate a model output. If the model output of the machine learning engine matches an application-specific condition, one or more of the other processing components are activated to execute an particular application corresponding to the application-specific condition.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 14, 2021
    Assignee: Google LLC
    Inventors: Lawrence J. Madar, III, Manu Gulati
  • Publication number: 20210341317
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. de Cesare, Anand Dalal
  • Publication number: 20210333132
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. de Cesare, Anand Dalal, Michael F. Culbert
  • Patent number: 11138346
    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: October 5, 2021
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Joseph Sokol, Jr., Jeffrey R. Wilcox, Bernard J. Semeria, Michael J. Smith
  • Publication number: 20210287677
    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 16, 2021
    Inventors: Timothy J. Millet, Manu Gulati, Michael F. Culbert
  • Publication number: 20210255972
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.
    Type: Application
    Filed: December 31, 2020
    Publication date: August 19, 2021
    Inventors: Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao, Benjamin Dodge, Albert Meixner, Allan Douglas Knies, Manu Gulati, Rahul Jagdish Thakur, Jason Rupert Redgrave
  • Patent number: 11079261
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 3, 2021
    Assignee: Apple Inc.
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. de Cesare, Anand Dalal
  • Patent number: 11049503
    Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: June 29, 2021
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Manu Gulati, Michael F. Culbert
  • Patent number: 10929222
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 23, 2021
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10884959
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 5, 2021
    Assignee: Google LLC
    Inventors: Vinod Chamarty, Xiaoyu Ma, Hongil Yoon, Keith Robert Pflederer, Weiping Liao, Benjamin Dodge, Albert Meixner, Allan Douglas Knies, Manu Gulati, Rahul Jagdish Thakur, Jason Rupert Redgrave
  • Patent number: 10877688
    Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 29, 2020
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Peter F. Holland, Erik P. Machnicki, Robert E. Jeter, Rakesh L. Notani, Neeraj Parik, Marc A. Schaub
  • Patent number: 10802968
    Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: October 13, 2020
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Gurjeet S. Saund, Manu Gulati, Shinye Shiu
  • Patent number: 10795818
    Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: October 6, 2020
    Assignee: Apple Inc.
    Inventors: Harshavardhan Kaushikkar, Per H. Hammarlund, Brian P. Lilly, Michael Bekerman, James Vash, Manu Gulati, Benjamin K. Dodge
  • Publication number: 20200278738
    Abstract: Methods, systems, and apparatus, for handling applications in an ambient computing system. One of the methods includes determining, by a low-power processing component, that particular sensor signals have a particular property. In response, a machine learning engine performs an inference pass over a machine learning model using the sensor signals to generate a model output. If the model output of the machine learning engine matches an application-specific condition, one or more of the other processing components are activated to execute an particular application corresponding to the application-specific condition.
    Type: Application
    Filed: November 21, 2018
    Publication date: September 3, 2020
    Inventors: Lawrence J. Madar, III, Manu Gulati