Patents by Inventor Manu Gulati

Manu Gulati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9549373
    Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 17, 2017
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Gilbert H. Herbeck
  • Patent number: 9529403
    Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Parin Patel, Keith Cox, Derek Iwamoto, Cyril de la Cropte de Chanterac, Christopher J. Young
  • Publication number: 20160328322
    Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.
    Type: Application
    Filed: May 6, 2015
    Publication date: November 10, 2016
    Inventors: Sukalpa Biswas, Harshavardhan Kaushikkar, Munetoshi Fukami, Gurjeet S. Saund, Manu Gulati, Shinye Shiu
  • Publication number: 20160313396
    Abstract: An integrated circuit (IC) having a bridge for interfacing a debugger and method of operating the same is provided. In one embodiment, an IC includes a debug control circuit and a debug interface block (DIB) implemented thereon. The DIB is coupled to the debug control circuit. The IC also includes an interface for a debugger and a number of interfaces for external circuits, each of the interfaces being coupled to the debug control circuit. The debug control circuit may function as a bridge for coupling an external debugger to the DIB and to external circuits coupled to the IC through corresponding ones of the interfaces. The debug control circuit may establish a connection between the debugger and one of the external circuits. Communications between the debugger and the external circuit may be conducted while bypassing the DIB.
    Type: Application
    Filed: April 22, 2015
    Publication date: October 27, 2016
    Inventors: James D. Ramsay, Manu Gulati, Mitchell Palmer Lichtenberg, JR.
  • Publication number: 20160240193
    Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Manu Gulati, Gilbert H. Herbeck, Alexei E. Kosut, Girault W. Jones, Timothy J. Millet
  • Patent number: 9378150
    Abstract: Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: June 28, 2016
    Assignee: Apple Inc.
    Inventors: Rohit K. Gupta, Manu Gulati
  • Publication number: 20160116969
    Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Sukalpa Biswas, Shinye Shiu, Cyril de la Cropte de Chanterac, Manu Gulati, Pulkit Desai, Rong Zhang Hu
  • Publication number: 20160091954
    Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Cyril de la Cropte de Chanterac, Manu Gulati, Erik P. Machnicki, Keith Cox, Timothy J. Millet
  • Publication number: 20160077579
    Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Manu Gulati, Tristan R. Hudson, Parin Patel, Fabien Faure
  • Patent number: 9280471
    Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 8, 2016
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Harshavardhan Kaushikkar, Gurjeet S. Saund, Wei-Han Lien, Gerard R. Williams, III, Sukalpa Biswas, Brian P. Lilly, Shinye Shiu
  • Publication number: 20160054788
    Abstract: A method and apparatus for parameter-based sensor selection is disclosed. In one embodiment, a system includes an integrated circuit (IC) having a first power management circuit, and a second power management circuit external to the IC. The IC includes various functional units implemented in various power domains, while the second power management circuit (which may be implemented on an IC) includes a number of voltage regulators for providing power to the power domains. The second power management circuit also includes sensors that provide data about a system parameter, with the data being provided at telemetry to the first power management circuit. When the system parameter is less than a first threshold, the telemetry data may be based on a first sensor. When the system parameter is greater than the first threshold, the telemetry data may be based on a second sensor.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Manu Gulati, Parin Patel, Derek Iwamoto, Carl D. Tappan
  • Publication number: 20160054773
    Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Manu Gulati, Parin Patel, Keith Cox, Derek Iwamoto, Cyril de la Cropte de Chanterac, Christopher J. Young
  • Publication number: 20160055110
    Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Gilbert H. Herbeck, Munetoshi Fukami, Manu Gulati
  • Publication number: 20160049207
    Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 18, 2016
    Inventors: Manu Gulati, Erik P. Machnicki, Gilbert H. Herbeck
  • Patent number: 9261939
    Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: February 16, 2016
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Shinye Shiu, Cyril de la Cropte de Chanterac, Manu Gulati, Pulkit Desai, Rong Zhang Hu
  • Publication number: 20160029318
    Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.
    Type: Application
    Filed: July 28, 2014
    Publication date: January 28, 2016
    Inventors: Manu Gulati, Gilbert H. Herbeck
  • Patent number: 9229894
    Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: January 5, 2016
    Assignee: Apple Inc.
    Inventors: Deniz Balkan, Gurjeet S Saund, Joseph P Bratt, Kevin C Wong, Manu Gulati, Rohit K Gupta
  • Publication number: 20150347287
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Application
    Filed: August 13, 2014
    Publication date: December 3, 2015
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. De Cesare, Anand Dalal
  • Publication number: 20150346001
    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
    Type: Application
    Filed: August 13, 2014
    Publication date: December 3, 2015
    Inventors: Brijesh Tripathi, Shane J. Keil, Manu Gulati, Jung Wook Cho, Erik P. Machnicki, Gilbert H. Herbeck, Timothy J. Millet, Joshua P. de Cesare, Anand Dalal
  • Patent number: 9201821
    Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 1, 2015
    Assignee: Apple Inc.
    Inventors: Erik P. Machnicki, Josh P. de Cesare, Manu Gulati