Abstract: A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.

Abstract: A system for hyper-dimensional computing for inference tasks may be provided. The device comprises an item memory for storing hyper-dimensional item vectors, a query transformation unit connected to the item memory, the query transformation unit being adapted for forming a hyper-dimensional query vector from a query input and hyper-dimensional base vectors stored in the item memory, and an associative memory adapted for storing a plurality of hyper-dimensional profile vectors and for determining a distance between the hyper-dimensional query vector and the plurality of hyper-dimensional profile vectors, wherein the item memory and the associative memory are adapted for in-memory computing using memristive devices.

Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.

Abstract: A device for hyper-dimensional computing may be provided. The device comprises a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors, of the resistive memory device, wherein the resistive memory device comprises a first crossbar array of the components, wherein the components are memristive 2D components addressable by word-lines and bit-lines, and a peripheral circuit connected to the word-lines and bit-lines and adapted for encoding operations by activating the word-lines and bit-lines sequentially in a predefined manner.

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n?1 and (p+n+m)=N where m?0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.

Abstract: Methods are provided for training weights of an artificial neural network to be implemented by inference computing apparatus in which the trained weights are stored as programmed conductance states of respective predetermined memristive devices. Such a method includes deriving for the memristive devices a probability distribution indicating distribution of conductance errors for the devices in the programmed conductance states. The method further comprises, in a digital computing apparatus: training the weights via an iterative training process in which the weights are repeatedly updated in response to processing by the network of training data which is propagated over the network via the weights; and applying noise dependent on said probability distribution to weights used in the iterative training process.

Abstract: A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

Abstract: Methods and apparatus are provided for training an artificial neural network, having a succession of neuron layers with interposed synaptic layers each storing a respective set of weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for at least one of the synaptic layers, providing a plurality P1 of arrays of memristive devices, each array storing the set of weights of that synaptic layer S1 in respective memristive devices, and, in a signal propagation operation, supplying respective subsets of the signals to be weighted by the synaptic layer S1 in parallel to the P1 arrays. The method also includes, in a weight-update calculation operation, calculating updates to respective weights stored in each of the P1 arrays in dependence on signals propagated by the neuron layers.

Abstract: A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.

Abstract: A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.

Abstract: A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector.

Abstract: A computer-implemented method of mixed-precision deep learning with multi-memristive synapses may be provided. The method comprises representing, each synapse of an artificial neural network by a combination of a plurality of memristive devices, wherein each of the plurality of memristive devices of each of the synapses contributes to an overall synaptic weight with a related device significance, accumulating a weight gradient ?W for each synapse in a high-precision variable, and performing a weight update to one of the synapses using an arbitration scheme for selecting a respective memristive device, according to which a threshold value related to the high-precision variable for performing the weight update is set according to the device significance of the respective memristive device selected by the arbitration schema.

Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.

Abstract: A multiplication device for performing a matrix-vector-multiplication may be provided. The multiplication device comprises a memristive crossbar array comprising a plurality of memristive devices. The device comprises a decomposition unit adapted for decomposing a matrix into a partial sum of multiple sub-matrices, and decomposing a vector into a sum of multiple sub-vectors, a programming unit adapted for programming the plurality of the memristive devices with values representing elements of the sub-matrices such that each one of the memristive devices corresponds to one of the elements of the sub-matrices, an applying unit adapted for applying elements of one of the multiple sub-vectors as input values to the memristive crossbar array to input lines of the memristive crossbar array resulting in partial results at output lines of the memristive crossbar array, and a summing unit adapted for scaling and summing the partial results building the product of the matrix and the vector.

Abstract: A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Abstract: A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Abstract: A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.