Patents by Inventor Manuel Le Gallo
Manuel Le Gallo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10423878Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.Type: GrantFiled: September 7, 2016Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
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Publication number: 20190287613Abstract: A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Inventors: Manuel Le Gallo-Bourdeau, Abu Sebastian, Giovanni Cherubini
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Publication number: 20190272464Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.Type: ApplicationFiled: April 18, 2019Publication date: September 5, 2019Inventors: Evangelos S. Eleftheriou, Lukas Kull, Manuel Le Gallo-Bourdeau, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
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Publication number: 20190188242Abstract: A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Inventors: Manuel Le Gallo, Abu Sebastian
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Publication number: 20190179872Abstract: A multiplication device for performing a matrix-vector-multiplication may be provided. The multiplication device comprises a memristive crossbar array comprising a plurality of memristive devices. The device comprises a decomposition unit adapted for decomposing a matrix into a partial sum of multiple sub-matrices, and decomposing a vector into a sum of multiple sub-vectors, a programming unit adapted for programing the plurality of the memristive devices with values representing elements of the sub-matrices such that each one of the memristive devices corresponds to one of the elements of the sub-matrices, an applying unit adapted for applying elements of one of the multiple sub-vectors as input values to the memristive crossbar array to input lines of the memristive crossbar array resulting in partial results at output lines of the memristive crossbar array, and a summing unit adapted for scaling and summing the partial results building the product of the matrix and the vector.Type: ApplicationFiled: February 15, 2019Publication date: June 13, 2019Inventors: Konstantinos Bekas, Alessandro Curioni, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Adelmo Cristiano Innocenza Malossi, Abu Sebastian
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Patent number: 10311126Abstract: A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector.Type: GrantFiled: August 12, 2016Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Manuel Le Gallo, Abu Sebastian
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Publication number: 20190122105Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method includes performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by applying input signals, associated with respective neurons, to row or column lines of the set of arrays to obtain output signals on the other of the row or column lines, and storing digital signal values corresponding to the input and output signals. The weight-update operation is performed by calculating digital weight-correction values for respective memristive devices, and applying programming signals to those devices to update the stored weights.Type: ApplicationFiled: June 29, 2018Publication date: April 25, 2019Inventors: IREM BOYBAT KARA, EVANGELOS STAVROS ELEFTHERIOU, MANUEL LE GALLO-BOURDEAU, NANDAKUMAR SASIDHARAN RAJALEKSHMI, ABU SEBASTIAN
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Publication number: 20190122727Abstract: A sensor device comprising a computational memory and electronic circuitry. The sensor device is configured to receive an input signal, to compress the input signal into a compressed signal and to compute a reconstructed signal from the compressed signal. The electronic circuitry is configured to perform a reconstruction algorithm to compute the reconstructed signal. The computational memory is configured to compute the compressed signal and partial results of the reconstruction algorithm. A related method and a related design structure may be provided.Type: ApplicationFiled: July 10, 2018Publication date: April 25, 2019Inventors: Manuel Le Gallo-Bourdeau, Abu Sebastian, Giovanni Cherubini
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Patent number: 10248323Abstract: A computing system having a computational memory and a method configured to perform computations using an approximate message passing process. The system exploits memcomputing which is a prominent non-von Neumann computational approach expected to significantly improve an energy efficiency of computing systems. The computational memory includes at least one memristive array comprising a plurality of memristive devices arranged in a crossbar topology and the computing system may further comprise digital combinational control circuitry adapted to perform read and write operations on the at least one memristive array and to store at least one state variable of the approximate message passing process. An output of the at least one memristive array represents a result of a computation of the approximate message passing process. The control circuitry may comprise circuitry to iteratively perform computations that may not require high precision.Type: GrantFiled: September 23, 2016Date of Patent: April 2, 2019Assignee: International Business Machines CorporationInventors: Giovanni Cherubini, Manuel Le Gallo, Abu Sebastian
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Patent number: 10217046Abstract: A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage.Type: GrantFiled: November 5, 2015Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tomas Tuma
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Patent number: 10210138Abstract: A multiplication device for performing a matrix-vector-multiplication may be provided. The multiplication device comprises a memristive crossbar array comprising a plurality of memristive devices. The device comprises a decomposition unit adapted for decomposing a matrix into a partial sum of multiple sub-matrices, and decomposing a vector into a sum of multiple sub-vectors, a programming unit adapted for programming the plurality of the memristive devices with values representing elements of the sub-matrices such that each one of the memristive devices corresponds to one of the elements of the sub-matrices, an applying unit adapted for applying elements of one of the multiple sub-vectors as input values to the memristive crossbar array to input lines of the memristive crossbar array resulting in partial results at output lines of the memristive crossbar array, and a summing unit adapted for scaling and summing the partial results building the product of the matrix and the vector.Type: GrantFiled: July 19, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: Konstantinos Bekas, Alessandro Curioni, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Adelmo Cristiano Innocenza Malossi, Abu Sebastian
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Publication number: 20190026251Abstract: A multiplication device for performing a matrix-vector-multiplication may be provided. The multiplication device comprises a memristive crossbar array comprising a plurality of memristive devices. The device comprises a decomposition unit adapted for decomposing a matrix into a partial sum of multiple sub-matrices, and decomposing a vector into a sum of multiple sub-vectors, a programming unit adapted for programming the plurality of the memristive devices with values representing elements of the sub-matrices such that each one of the memristive devices corresponds to one of the elements of the sub-matrices, an applying unit adapted for applying elements of one of the multiple sub-vectors as input values to the memristive crossbar array to input lines of the memristive crossbar array resulting in partial results at output lines of the memristive crossbar array, and a summing unit adapted for scaling and summing the partial results building the product of the matrix and the vector.Type: ApplicationFiled: July 19, 2017Publication date: January 24, 2019Inventors: Konstantinos Bekas, Alessandro Curioni, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Adelmo Cristiano Innocenza Malossi, Abu Sebastian
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Patent number: 10114613Abstract: A computing system includes computational memory and digital combinational circuitry operatively coupled with the computational memory. The computational memory is configured to perform computations at a prescribed precision. The digital combinational circuitry is configured to increase the precision of the computations performed by the computational memory. The computational memory and the digital combinational circuitry may be configured to iteratively perform a computation to a predefined precision. The computational memory may include circuitry configured to perform analog computation using values stored in the computational memory, and the digital combinational circuitry may include a central processing unit, a graphics processing unit and/or application specific circuitry. The computational memory may include an array of resistive memory elements having resistance or conductance values stored therein, the respective resistance or conductance values being programmable.Type: GrantFiled: September 7, 2016Date of Patent: October 30, 2018Assignee: International Business Machines CorporationInventors: Konstantinos Bekas, Alessandro Curioni, Evangelos S. Eleftheriou, Manuel Le Gallo-Bourdeau, Abu Sebastian, Tomas Tuma
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Patent number: 10109725Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.Type: GrantFiled: June 22, 2017Date of Patent: October 23, 2018Assignee: ABB Schweiz AGInventors: Liutauras Storasta, Chiara Corvasce, Manuel Le Gallo, Munaf Rahimo, Arnost Kopta
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Patent number: 10079058Abstract: The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising of row lines, of columns lines and of junctions arranged between the row lines and the column lines. Each junction comprises a programmable resistive memory element. The device comprises a signal generator and a readout circuit. The device is configured to perform a calibration procedure to compensate for conductance variations of the resistive memory elements. The calibration procedure is configured to program a calibration subset of the plurality of resistive memory elements to initial conductance values and to apply a constant calibration voltage to the row lines of the calibration subset. The device is configured to read calibration current values of the column lines of the calibration subset and to derive an estimation of a conductance variation parameter from the calibration current values.Type: GrantFiled: August 24, 2017Date of Patent: September 18, 2018Assignee: International Business Machines CorporationInventors: Evangelos S. Eleftheriou, Manuel Le Gallo-Bourdeau, Abu Sebastian
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Patent number: 9996793Abstract: Method to produce a neuromorphic synapse apparatus comprising a memelement for storing a synaptic weight, and programming logic. The memelement is adapted to exhibit a desired programming characteristic. The programming logic is responsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement to update said weight. The programming logic may be responsive to an input signal indicating an input weight-change value ?Wi, and may be adapted to generate a programming signal dependent on the input weight-change value ?Wi. The programming logic is adapted such that the programming signals exploit the programming characteristic of the memelement to provide a desired weight-dependent synaptic update efficacy.Type: GrantFiled: July 21, 2015Date of Patent: June 12, 2018Assignee: International Business MachinesInventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tuma Tomas
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Patent number: 9990580Abstract: Neuromorphic synapse apparatus 11 comprises a memelement 20 for storing a synaptic weight, and programming logic 21. The memelement 20 is adapted to exhibit a desired programming characteristic. The programming logic 21 is responsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement 20 to update said weight. The programming logic 21 may be responsive to an input signal indicating an input weight-change value ?Wi, and may be adapted to generate a programming signal dependent on the input weight-change value ?Wi. The programming logic 21 is adapted such that the programming signals exploit the programming characteristic of the memelement 20 to provide a desired weight-dependent synaptic update efficacy.Type: GrantFiled: March 13, 2015Date of Patent: June 5, 2018Assignee: International Business Machines CorporationInventors: Evangelos S. Eleftheriou, Manuel Le Gallo, Angeliki Pantazi, Abu Sebastian, Tuma Tomas
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Publication number: 20180088801Abstract: A computing system having a computational memory and a method configured to perform computations using an approximate message passing process. The system exploits memcomputing which is a prominent non-von Neumann computational approach expected to significantly improve an energy efficiency of computing systems. The computational memory includes at least one memristive array comprising a plurality of memristive devices arranged in a crossbar topology and the computing system may further comprise digital combinational control circuitry adapted to perform read and write operations on the at least one memristive array and to store at least one state variable of the approximate message passing process. An output of the at least one memristive array represents a result of a computation of the approximate message passing process. The control circuitry may comprise circuitry to iteratively perform computations that may not require high precision.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Giovanni Cherubini, Manuel Le Gallo, Abu Sebastian
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Publication number: 20180082177Abstract: A method and system providing a multi-memristive synaptic element for a cognitive computing system. The multi-memristive synaptic element comprises an array of memristive devices. The method comprises arbitrating a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, updating said synaptic weight variable by a delta amount, and assigning said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element.Type: ApplicationFiled: August 18, 2017Publication date: March 22, 2018Inventors: Irem Boybat Kara, Manuel Le Gallo, Abu Sebastian, Tomas Tuma
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Publication number: 20180067720Abstract: A computing system includes computational memory and digital combinational circuitry operatively coupled with the computational memory. The computational memory is configured to perform computations at a prescribed precision. The digital combinational circuitry is configured to increase the precision of the computations performed by the computational memory. The computational memory and the digital combinational circuitry may be configured to iteratively perform a computation to a predefined precision. The computational memory may include circuitry configured to perform analog computation using values stored in the computational memory, and the digital combinational circuitry may include a central processing unit, a graphics processing unit and/or application specific circuitry. The computational memory may include an array of resistive memory elements having resistance or conductance values stored therein, the respective resistance or conductance values being programmable.Type: ApplicationFiled: September 7, 2016Publication date: March 8, 2018Inventors: Konstantinos Bekas, Alessandro Curioni, Evangelos S. Eleftheriou, Manuel Le Gallo-Bourdeau, Abu Sebastian, Tomas Tuma