Abstract: Artificial neuron apparatus includes first and second resistive memory cells. The first resistive memory cell is connected in first circuitry having a first input and output. The second resistive memory cell is connected in second circuitry having a second input and output. The first and second circuitry are operable in alternating read and write phases to apply a programming current to their respective memory cells on receipt of excitatory and inhibitory neuron input signals, respectively. During the write phase, resistance of the respective cells is changed in response to successive excitatory and inhibitory neuron input signals. During the read phase, a read current is applied to their respective cells to produce first and second measurement signals, respectively. An output circuit connected to the first and second outputs produces a neuron output signal at a neuron output when a difference between the first and second measurement signals traverses a threshold.

Abstract: Embodiments include a random number generation entity having at least one switching cell comprising a pair of electrodes and a chalcogenide layer arranged between the pair of electrodes and a pulse generating entity coupled with the electrodes of the switching cell. The pulse generating entity is configured to provide an excitation pulse to the switching cell. The random number generation entity also includes a detection entity configured to provide a detection signal indicating whether an electrical property measured at the switching cell exceeds or falls below a threshold value due to applying the excitation pulse to the switching cell and a random number generation entity adapted to generate a random number based on the detection signal of the detection entity.

Abstract: A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector.

Abstract: A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

Abstract: A system, method and computer program product for achieving a collective task. The system comprises a plurality of elements representative of a first hierarchy level, each element comprises a plurality of sub-elements. The system comprises also an arbitration module for selecting one of the sub-elements of each element at a point in time based on a global clock, wherein each sub-element relates to one list element of an ordered circular list, and a combination module adapted for a combination of sub-actions performed by a portion of the sub-elements of one of the elements over a predefined period of time, wherein each sub-element performs one of the sub-actions.

Abstract: A method and system providing a multi-memristive synaptic element for a cognitive computing system. The multi-memristive synaptic element comprises an array of memristive devices. The method comprises arbitrating a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, updating said synaptic weight variable by a delta amount, and assigning said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element.

Abstract: Embodiments include a random number generation entity having at least one switching cell comprising a pair of electrodes and a chalcogenide layer arranged between the pair of electrodes and a pulse generating entity coupled with the electrodes of the switching cell. The pulse generating entity is configured to provide an excitation pulse to the switching cell. The random number generation entity also includes a detection entity configured to provide a detection signal indicating whether an electrical property measured at the switching cell exceeds or falls below a threshold value due to applying the excitation pulse to the switching cell and a random number generation entity adapted to generate a random number based on the detection signal of the detection entity.

Abstract: A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

Abstract: A neuromorphic processing device has a device input, for receiving an input data signal, and an assemblage of neuron circuits. Each neuron circuit comprises a resistive memory cell which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals for programming cell resistance to vary the neuron state, and a neuron output circuit for supplying a neuron output signal in response to cell resistance traversing a threshold. The device includes an input signal generator, connected to the device input and the assemblage of neuron circuits, for generating neuron input signals for the assemblage in dependence on the input data signal. The device further includes a device output circuit, connected to neuron output circuits of the assemblage, for producing a device output signal dependent on neuron output signals of the assemblage, whereby the processing device exploits stochasticity of resistive memory cells of the assemblage.

Abstract: A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

Abstract: Method to produce a neuromorphic synapse apparatus comprising a memelement for storing a synaptic weight, and programming logic. The memelement is adapted to exhibit a desired programming characteristic. The programming logic is responsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement to update said weight. The programming logic may be responsive to an input signal indicating an input weight-change value ?Wi, and may be adapted to generate a programming signal dependent on the input weight-change value ?Wi. The programming logic is adapted such that the programming signals exploit the programming characteristic of the memelement to provide a desired weight-dependent synaptic update efficacy.

Abstract: Neuromorphic synapse apparatus 11 comprises a memelement 20 for storing a synaptic weight, and programming logic 21. The memelement 20 is adapted to exhibit a desired programming characteristic. The programming logic 21 is responsive to a stimulus prompting update of the synaptic weight for generating a programming signal for programming the memelement 20 to update said weight. The programming logic 21 may be responsive to an input signal indicating an input weight-change value ?Wi, and may be adapted to generate a programming signal dependent on the input weight-change value ?Wi. The programming logic 21 is adapted such that the programming signals exploit the programming characteristic of the memelement 20 to provide a desired weight-dependent synaptic update efficacy.

Abstract: A device for determining an actual level of a resistive memory cell having a plurality of programmable levels is suggested. The device comprises an estimator unit and a detection unit. The estimator unit is adapted to receive a time input signal and a temperature input signal and to estimate changes of a read-out signal of the levels of the resistive memory cell based on a time and temperature dependent model of the resistance changes, the received time input signal and the received temperature input signal. The detection unit is adapted to receive an actual read-out signal from the resistive memory cell and the estimated changes from the estimator unit. Further, the detection unit is adapted to determine the actual level of the resistive memory cell based on the received read-out signal and the received estimated changes.