Patents by Inventor Mao Hua
Mao Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961753Abstract: A substrate-bonding device includes a carrier, three first aligning units, three second aligning units, a pressing plate, and two flat-edge aligners. A carrying surface of the carrier is provided with a placement area for placing a first substrate provided with a flat edge thereon. The first aligning units, the second aligning units and the flat edge aligners are disposed around the placement area. The first aligning units are configured to align the first substrate and to support a second substrate provided with a second flat edge. The second aligning units are configured to align the second substrate. The flat edge aligners are configured to contact the first and the second flat edges, to position and align the first and the second substrates. The pressing plate is disposed to face the placement area for pressing the first and second substrates. The flat edge aligners move along with the pressing plate.Type: GrantFiled: December 10, 2021Date of Patent: April 16, 2024Assignee: SKY TECH INC.Inventors: Jing-Cheng Lin, Jung-Hua Chang, Mao-Chan Chang
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Patent number: 11942451Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
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Patent number: 11747382Abstract: Testing equipment is used in an antenna testing process, and includes a testing head having a perforation, and a testing device having a cylinder. The cylinder is disposed in the perforation to act as a cavity for the antenna testing process. Therefore, only the cylinder needs to be replaced when the antenna testing process is performed on different devices under test, with the whole testing head intact.Type: GrantFiled: December 20, 2019Date of Patent: September 5, 2023Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Bo-Siang Fang, Kuang-Sheng Wang, Hsinjou Lin, Shao-Meng Sim, Mao-Hua Yeh
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Patent number: 11461076Abstract: A method for editing continual vertical line of visual programming language includes following steps: entering an editing mode; selecting a source node as a current node from a serial-parallel graphic where the source node is an endpoint of one of a plurality of normal blocks in the graphic; calculating and displaying one or more candidate nodes around current node; connecting the current node to any one of the candidate nodes for converting the connected candidate node into a connected node; setting the connected node as the current node for continually calculating, displaying, connecting to one or more candidate nodes before exiting the editing mode; generating a continual vertical line according to the source node and the one or more connected nodes when exiting the editing mode; modifying the serial-parallel relationship among the plurality of normal blocks in the graphic and updating the graphic according to the continual vertical line.Type: GrantFiled: September 28, 2020Date of Patent: October 4, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Yung-Liang Chang, Mao-Hua Cheng, Kuei-Fu Liu
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Publication number: 20220139925Abstract: This application relates to a semiconductor memory device and a method of forming the same. The method includes the following steps: providing a substrate with a bit line contact area in the substrate, wherein the surface of the substrate is disposed with a dielectric layer; forming a through trench penetrating the dielectric layer and exposing the bit line contact area; filling a first conductive material in the trench to forum a bit line, wherein the top surface of the bit line is configured to be lower than the top surface of the dielectric layer; filling an insulating material in the trench to form a bit line cap layer on the top surface of the bit line. This application does not cause misalignment problem due to the small line width of the bit line and in addition, reduces the internal resistance inside the memory device.Type: ApplicationFiled: May 29, 2020Publication date: May 5, 2022Inventor: Mao-Hua Su
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Publication number: 20220025257Abstract: Ternary transition metal halides are described herein. The ternary transition metal halides may be used as scintillator materials.Type: ApplicationFiled: April 26, 2021Publication date: January 27, 2022Inventors: Luis Stand Stracuzzi, Mao-Hua Du, Edgar V. Van Loef, Merry A. Koschan, Mariya Zhuravleva, Charles L. Melcher, Kanai S. Shah
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Publication number: 20220005786Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: ApplicationFiled: September 22, 2021Publication date: January 6, 2022Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
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Patent number: 11152331Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: GrantFiled: November 4, 2019Date of Patent: October 19, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
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Patent number: 11081415Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: GrantFiled: April 29, 2020Date of Patent: August 3, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20210149642Abstract: A method for editing continual vertical line of visual programming language includes following steps: entering an editing mode; selecting a source node as a current node from a serial-parallel graphic where the source node is an endpoint of one of a plurality of normal blocks in the graphic; calculating and displaying one or more candidate nodes around current node; connecting the current node to any one of the candidate nodes for converting the connected candidate node into a connected node; setting the connected node as the current node for continually calculating, displaying, connecting to one or more candidate nodes before exiting the editing mode; generating a continual vertical line according to the source node and the one or more connected nodes when exiting the editing mode; modifying the serial-parallel relationship among the plurality of normal blocks in the graphic and updating the graphic according to the continual vertical line.Type: ApplicationFiled: September 28, 2020Publication date: May 20, 2021Inventors: Yung-Liang CHANG, Mao-Hua CHENG, Kuei-Fu LIU
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Publication number: 20210123962Abstract: Testing equipment is used in an antenna testing process, and includes a testing head having a perforation, and a testing device having a cylinder. The cylinder is disposed in the perforation to act as a cavity for the antenna testing process. Therefore, only the cylinder needs to be replaced when the antenna testing process is performed on different devices under test, with the whole testing head intact.Type: ApplicationFiled: December 20, 2019Publication date: April 29, 2021Inventors: Bo-Siang Fang, Kuang-Sheng Wang, Hsinjou Lin, Shao-Meng Sim, Mao-Hua Yeh
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Publication number: 20200388591Abstract: An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.Type: ApplicationFiled: November 4, 2019Publication date: December 10, 2020Inventors: Lung-Yuan Wang, Feng Kao, Mao-Hua Yeh
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Patent number: 10833394Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.Type: GrantFiled: August 7, 2019Date of Patent: November 10, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Jung Tsai, Mao-Hua Yeh, Chih-Hsien Chiu, Ying-Chou Tsai, Chun-Chi Ke
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Publication number: 20200342991Abstract: Presented are concepts for detecting recurrence of a medical condition in a subject previously treated for the medical condition. One such concept comprises, using natural language processing, extracting information from a data set comprising information relating to the subject prior to and/or during the subject's previous treatment for the medical condition. The extracted information is reformulated into structured data based on a standardized model. A data retrieval request comprising a structured query adhering to a template is obtained and, based on the structured query of the data retrieval request, data is retrieved from the structured data.Type: ApplicationFiled: January 16, 2019Publication date: October 29, 2020Inventors: Yiyi Hu, Yan Li, Zuofeng Li, Huichuan Sun, Mao Hua Yang, Jian Zhou, Jia Fan
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Publication number: 20200258802Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20200235462Abstract: An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.Type: ApplicationFiled: August 7, 2019Publication date: July 23, 2020Inventors: Wen-Jung Tsai, Mao-Hua Yeh, Chih-Hsien Chiu, Ying-Chou Tsai, Chun-Chi Ke
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Patent number: 10679914Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: GrantFiled: June 28, 2017Date of Patent: June 9, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh
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Publication number: 20180293620Abstract: A method and system that provides a user with precision and accuracy of recommended information that matches the user's personality and behavior by obtaining the location of the user's mobile terminal, determining a target area based on the location, the target area including more than one signal transmission source, each signal transmission source carrying an ID that represents the signal transmission source, and the ID carried in the signal transmission source being transmitted within a target range by using the signal transmission source, obtaining other information from the terminal including user basic information and/or user behavior information and/or user relation chain information, selecting target display information associated with this information from the display information associated with the more than one ID of the terminal, and sending the target display information to the terminal.Type: ApplicationFiled: June 8, 2018Publication date: October 11, 2018Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventor: Mao Hua CHEN
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Publication number: 20180254232Abstract: The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.Type: ApplicationFiled: June 28, 2017Publication date: September 6, 2018Inventors: Chieh-Lung Lai, Cheng-Yi Chen, Chun-Hung Lu, Mao-Hua Yeh