Patents by Inventor Marc Duranton

Marc Duranton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11308388
    Abstract: A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: April 19, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Marc Philippe, Alexandre Carbon, Marc Duranton
  • Patent number: 11222254
    Abstract: A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 11, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alexandre Carbon, Olivier Bichler, Marc Duranton, Jean-Marc Philippe
  • Patent number: 11182170
    Abstract: A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stéphane Chevobbe, Marc Duranton
  • Publication number: 20210240482
    Abstract: A processor having a SIMD architecture, including an array of elementary processors, each elementary processor being associated with an elementary memory cell, a central controller connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction including a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.
    Type: Application
    Filed: June 6, 2019
    Publication date: August 5, 2021
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stéphane CHEVOBBE, Marc DURANTON
  • Patent number: 11080593
    Abstract: An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 3, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Marc Duranton, Jean-Marc Philippe, Michel Paindavoine
  • Patent number: 11017290
    Abstract: A signal processing module comprises at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for the computation units, the memory being organized so that each data word is stored column-wise over several addresses according to an order dependent on the application, a column having a width of one bit, the words being transferred in series to the computation units.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: May 25, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Marc Duranton, Jean-Marc Philippe
  • Patent number: 10271051
    Abstract: A method implemented by a processor for coding a real signal, for example an image signal, into a quantized signal, comprises the following steps applied to each real sample of the real signal: converting the real sample into a digital representation, selecting, in the fractional part of the number, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining its distance Pi with respect to the neighboring selected non-zero significant bit of higher rank or, for the first non-zero significant bit selected, with respect to the decimal point, deducting from the distance Pi the minimum value of distance between two non-zero bits, coding the modified distance Pi on a predetermined number Mi of bits.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 23, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Hong-Phuc Trinh, Marc Duranton, Michel Paindavoine
  • Publication number: 20190005378
    Abstract: A circuit comprises a series of calculating blocks that can each implement a group of neurons; a transformation block that is linked to the calculating blocks by a communication means and that can be linked at the input of the circuit to an external data bus, the transformation block transforming the format of the input data and transmitting the data to said calculating blocks by means of K independent communication channels, an input data word being cut up into sub-words such that the sub-words are transmitted over multiple successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel dedicated to the word such that the N channels can transmit K words in parallel.
    Type: Application
    Filed: December 7, 2016
    Publication date: January 3, 2019
    Inventors: Jean-Marc PHILIPPE, Alexandre CARBON, Marc DURANTON
  • Publication number: 20180373977
    Abstract: A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.
    Type: Application
    Filed: December 7, 2016
    Publication date: December 27, 2018
    Applicant: COMMISSARIAT A L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Alexandre CARBON, Olivier BICHLER, Marc DURANTON, Jean-Marc PHILIPPE
  • Patent number: 9864722
    Abstract: A communication system coupled to a data-acquisition circuit and to a data-processing circuit is provided, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in the shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. Methods for communication between a data-acquisition circuit and a data-processing circuit are also provided.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 9, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Stephane Chevobbe, Marc Duranton
  • Publication number: 20170302933
    Abstract: A method implemented by a processor for coding a real signal, for example an image signal, into a quantized signal, comprises the following steps applied to each real sample of the real signal: converting the real sample into a digital representation, selecting, in the fractional part of the number, a predetermined number N of most significant non-zero bits, for each non-zero significant bit i selected, i varying from 1 to N, determining its distance Pi with respect to the neighboring selected non-zero significant bit of higher rank or, for the first non-zero significant bit selected, with respect to the decimal point, deducting from the distance Pi the minimum value of distance between two non-zero bits, coding the modified distance R on a predetermined number Mi of bits.
    Type: Application
    Filed: September 24, 2015
    Publication date: October 19, 2017
    Inventors: Hong-Phuc TRINH, Marc DURANTON, Michel PAINDAVOINE
  • Patent number: 9532030
    Abstract: A three-dimensional scene sensor comprises: a deformable optical system modifying focal distance by control signal, optics imaging the scene by analog image sensor for depths corresponding to distances; the image sensor comprising a matrix of pixels grouped into sub-matrices of macro-pixels being a sub-assembly of pixels, each macro-pixel operating independently for acquisition and reading of data; a matrix of elementary processors, each macro-pixel directly connected to a dedicated processor wherein pixel data for the macro-pixel are transmitted and processed by the processor, each processor carries out, for each pixel, local processing operations calculating depth information for macro-pixel, the processors operating in parallel and independently such that the depth information is processed and calculated in parallel over all macro-pixels of the image sensor, the processors connected to at least one processing unit allowing calculations using high-level input data, calculated starting from the pixel data di
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: December 27, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Anthony Kolar, Marc Duranton
  • Publication number: 20160292566
    Abstract: A signal processing module comprises at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for the computation units, the memory being organized so that each data word is stored column-wise over several addresses according to an order dependent on the application, a column having a width of one bit, the words being transferred in series to the computation units.
    Type: Application
    Filed: November 27, 2014
    Publication date: October 6, 2016
    Inventors: Marc DURANTON, Jean-Marc PHILIPPE
  • Publication number: 20160203401
    Abstract: An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.
    Type: Application
    Filed: September 29, 2014
    Publication date: July 14, 2016
    Inventors: Marc DURANTON, Jean-Marc PHILIPPE, Michel PAINDAVOINE
  • Publication number: 20150212970
    Abstract: The present invention relates to a communication system coupled to a data-acquisition circuit and to a data-processing circuit, including at least one shift register, an addressing circuit and a multiplexer. The shift register includes a serial input for inputting and storing data in series, a serial output for outputting data in series, and parallel outputs for outputting data stored in said shift register in parallel. The addressing circuit is coupled to the shift register in order to identify the positions of stored data, and the multiplexer is coupled to the parallel outputs of the shift register in order to output the stored data to the data-processing circuit in series. The present invention also relates to methods for communication between a data-acquisition circuit and a data-processing circuit.
    Type: Application
    Filed: December 14, 2012
    Publication date: July 30, 2015
    Inventors: Stéphane Chevobbe, Marc Duranton
  • Patent number: 8909577
    Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analog pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: December 9, 2014
    Assignee: Commissariat à l'énergie et aux énergies alternatives
    Inventors: Rodolphe Heliot, Marc Duranton, Antoine Joubert
  • Publication number: 20140354778
    Abstract: A three-dimensional scene sensor comprises: a deformable optical system modifying focal distance by control signal, optics imaging the scene by analog image sensor for depths corresponding to distances; the image sensor comprising a matrix of pixels grouped into sub-matrices of macro-pixels being a sub-assembly of pixels, each macro-pixel operating independently for acquisition and reading of data; a matrix of elementary processors, each macro-pixel directly connected to a dedicated processor wherein pixel data for the macro-pixel are transmitted and processed by the processor, each processor carries out, for each pixel, local processing operations calculating depth information for macro-pixel, the processors operating in parallel and independently such that the depth information is processed and calculated in parallel over all macro-pixels of the image sensor, the processors connected to at least one processing unit allowing calculations using high-level input data, calculated starting from the pixel data di
    Type: Application
    Filed: December 13, 2012
    Publication date: December 4, 2014
    Inventors: Anthony Kolar, Marc Duranton
  • Publication number: 20130185237
    Abstract: A neuromorphic data processing device comprising a plurality of spiking neurons, with each of these neurons comprising: an integrator designed to receive successive analogue pulses each having a certain value, and accumulate the values of the pulses received in a recorded value, referred to as accumulation value, and a discharger designed to emit a pulse, referred to as discharge pulse, according to the accumulation value, and a silicon support having two surfaces, the neurons being carried out on at least one of the two surfaces, the integrator of each neuron comprising a metal via of the TSV type between the two surfaces of the silicon support, the metal via of the TSV type forming a capacitor with the silicon support and having an electric potential forming the accumulation value wherein the values of the pulses received are accumulated and according to which the discharge pulse is emitted.
    Type: Application
    Filed: July 16, 2012
    Publication date: July 18, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: Rodolphe HELIOT, Marc Duranton, Antoine Joubert
  • Patent number: 8452827
    Abstract: The invention relates to a data processing system for performing a polyphase filtering. This circuit comprises functional units (304, 305, 306) able to perform polyphase filterings, and a memory device (301, 302, 308) for storing data and coefficients. The functional units receive in parallel data and coefficients coming from the memory device, calculate results from the data and coefficients and supply these results to the memory device.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: May 28, 2013
    Assignee: Entropic Communications, Inc.
    Inventors: Marc Duranton, Laurent Pasquier, Valérie Rivierre, Qin Zhao
  • Patent number: 7319697
    Abstract: The present invention relates to a communicating data system comprising devices (11, 12, 13, 14) for routing said data that are interconnected by communication links, the data being transmitted in packets and a packet comprising a header. A transmitting part of a first routing device (12) comprises first storage means suitable for storing a value of at least one parameter from said header and for transmitting a coded value corresponding thereto, and first entropy coding compression means which are suitable for recoding the uncoded value, the recoded value being stored instead of the coded value after the latter is transmitted along a communication link (15).
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: January 15, 2008
    Assignee: NXP B.V.
    Inventors: Marc Duranton, Laurent Pasquier, Valerie Rivierre, Qin Zhao