Abstract: A data processing arrangement (1) comprises a first processor (PROC1) for providing successive sets of input data, a second processor (PROC2) for receiving successive sets of output data and a memory system (2) comprising a plurality of memory circuits (MEM) for storing the input and output data. According to the invention, the data processing arrangement further comprises a master controller (MCP) for setting up the memory system by means of control commands (CC) associated with a set of input data and a set of output data. These control commands are received in the memory system by a control unit (MCU). When a data (Di) from the set of input data is provided by the first processor, this control unit selects, on the basis of the control commands, a first memory circuit and generates a write-address (AD_W) in said first memory circuit.

Abstract: A method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor, comprises a step of planning 10 in the course of which an order and a timing of said operations are established, a step of estimating 13 a retention time specific to each variable, a step of forecasting 14 at least one instant at which each variable must be refreshed, a step of placement 15 in the course of which the variables are placed in the memory, a step of refreshing 16 in the course of which the variables are refreshed at the instants defined during the forecasting step 14. The invention allows a reduction in the latency times and in the consumption of current which are related to the refreshing. It is of particular benefit in systems where the real time constraint is important, for example video data processing systems.

Abstract: A data-processing arrangement for a plurality of parallel data processors is disclosed. An operation carried out by at least one of the parallel processors is defined by an instruction word or code. The data-processing arrangement includes a control processor that makes compositions of instruction words using instruction-word composing software. A composition (VLIW) of instruction words defines operations which are to be carried out in parallel. The compositions are then provided to each parallel data processor as required. Storage of instruction-word composing software generally requires less memory space than storage of independent VLIW-s for each parallel data processor. The cost-saving this provides generally outweighs any additional costs associated with providing the control processor. Thus, the data-processing arrangement yields better cost and memory efficiency.

Abstract: The invention relates to a method of communication between terminals and a central server, in which these terminals, whose principal function is MPEG-2 decoding, are diverted from this function, on request and after authorization, in order to partake in parallel in the common implementation of an auxiliary function under control of said server.

Abstract: A method is described for addressing units (FU1, FU2, FU3) amongst a plurality of units having different addresses (ADD1, ADD2, ADD3) by use of an address word (AW), the addresses and the address word being composed of address elements. A tag word (TW) is transmitted to the plurality of units, the tag word defining which address elements of the address word are significant (S) and which address elements of the address word are non significant (X). The address word and the addresses of the units are compared and, a unit is addressed if the significant elements of the address word match the corresponding elements of the unit's address.

Abstract: A data processing arrangement comprises various data processors (P) and a memory arrangement (MA) for supplying input data (Di) to the data processors (P) and for storing output data (Do) from the data processors (P). The following steps are alternately carried out: a configuring step (CS) and a processing step (PS). In a configuration step (CS), the data processing arrangement is configured such that each data processor (P) will process a block (B) of data contained in the memory arrangement (MA) and then stop processing data. In a processing step (PS), the blocks (B) of data are processed in the respective data processors (P). A subsequent configuring step (CS) is carried out only when each data processor (P) has processed its block (B) of data (∀P: B=PROC>CS). Such a data processing arrangement allows great versatility because different data processing chains can be realized without this requiring relatively complicated software.

Abstract: A data processing device, including a plurality (VP) of elementary processors (EP) which operate in parallel in a so-called common instruction mode acting on multiple data, and means (VSU) for collectively processing data (OB1-OBn) supplied by said elementary processors. The device includes a concatenated data path (DP) enabling an arbitrary elementary processor to communicate with at least one adjoining elementary processor. Input and output controllers (13,19) enable communication with a common input bus (ID). The processing utilizes vector-scalar transformation units (VSU), scalar-vector units (SVCU) and scalar-scalar units (SSU). Each device comprises an interface for connection to either other, identical devices or to external members (memory, controller, data look-up table . . . ).

Abstract: The device is adapted more particularly to process programs written in FORTH. The device includes a) a program memory (1) storing instruction data, b) an operational unit (15) comprising a plurality of operational means (16, 17, 18), c) a central decoding unit (35), and d) a stack memory (8) for the return instructions.

Abstract: Data processing device, more particularly adapted to a chained language, especially of the FORTH type.This data processing device, more particularly adapted to a chained computer language, especially of the FORTH type includes:a main memory (10) for containing an execution program with its instruction data formed by a plurality of instructions which are directly executable or indirectly executable, the latter being arranged in at least one sub-program,a first stack-type memory (30) for containing the address following the address calling a sub-program (return address),one or several operational units (40) for executing the instructions which can be directly executed, each of which may contain:a second stack-type memory (20) for containing parameters used by the said program,an instruction-decoding member (40) for decoding each instruction data coming from the main memory.

Abstract: A neural network system comprises a memory for storing in binary code the synaptic coefficients indicative of the interconnections among the neurons. Means are provided for simultaneously supplying all the synaptic coefficients associated with a given neuron. Digital multipliers are provided for determining the product of the supplied synaptic coefficients and the relevant neuron states of the neurons connected to said given neuron. The multipliers deliver their results into an adder tree for determining the sum of the products. As a result of the parallel architecture of the system high operating speeds are attainable. The modular architecture enables extension of the system.