Abstract: The present invention relates to a communicating data system comprising devices (11, 12, 13, 14) for routing said data that are interconnected by communication links, the data being transmitted in packets and a packet comprising a header. A transmitting part of a first routing device (12) comprises first storage means suitable for storing a value of at least one parameter from said header and for transmitting a coded value corresponding thereto, and first entropy coding compression means which are suitable for recoding the uncoded value, the recoded value being stored instead of the coded value after the latter is transmitted along a communication link (15).

Abstract: The invention relates to a processing system comprising a calculation device comprising at least one calculation unit (13), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the switching system, the storage device comprises several banks of registers (21, 22) for storing words, the switching system comprises at least one switching device (24) associated with each bank of registers and the calculation units exchange a word with a bank of registers by means of the associated switching device.

Abstract: The present invention relates to a converter converting an input digital signal into an output digital signal. Said converter comprises in particular a set of shift registers able to contain samples of the input or output digital signal. It also comprises a calculation unit able to supply a shift signal (4) to said set of registers. Said calculation unit comprises a first storage unit (51) able to contain a value of a conversion ratio or of its inverse, so that the value stored is between 0 and 1. It also comprises a second storage unit (52) able to contain, at a cycle time i+1, i being an integer, a future signal (8) equal to a sum of a current signal (7) contained in the second unit at a cycle time i and of the content of the first storage unit. The shift signal then results from an exclusive OR function (54) between a most significant bit of the current signal (71) and a most significant bit of the future signal (81).

Abstract: The invention relates to a method of tracing and filling in a parallelogram (ABCD), comprising a first vertex (A), a second vertex (B), a third vertex (C) and a fourth vertex (D) on a discrete grid of a graphics screen from knowledge of the coordinates of its vertices. The method according to the invention comprises a step (10) of calculating the coordinates of the points on a first segment (AB) between the first vertex (A) and the second vertex (B), a step (11) of calculating the coordinates of the points on a second segment (AC) between the first vertex (A) and the third vertex (C), a step (12) of calculating the coordinates of the points on a third segment (BD) between the second vertex (BD) and the fourth vertex D and an iterative step (20) of calculating the coordinates of the points on a segment parallel to the segment AB and included within the parallelogram ABCD.

Abstract: The present invention relates to a converter converting an input digital signal into an output digital signal. Said converter comprises in particular a set of shift registers able to contain samples of the input or output digital signal. It also comprises a calculation unit able to supply a shift signal (4) to said set of registers. Said calculation unit comprises a first storage unit (51) able to contain a value of a conversion ratio or of its inverse, so that the value stored is between 0 and 1. It also comprises a second storage unit (52) able to contain, at a cycle time i+1, i being an integer, a future signal (8) equal to a sum of a current signal (7) contained in the second unit at a cycle time i and of the content of the first storage unit. The shift signal then results from an exclusive OR function (54) between a most significant bit of the current signal (71) and a most significant bit of the future signal (81).

Abstract: The invention relates to a data processing system for performing a polyphase filtering. This circuit comprises functional units (304, 305, 306) able to perform polyphase filterings, and a memory device (301, 302, 308) for storing data and coefficients. The functional units receive in parallel data and coefficients coming from the memory device, calculate results from the data and coefficients and supply these results to the memory device.

Abstract: The invention relates to a processing system comprising a calculation device comprising at least one calculation unit (13), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the switching system, the storage device comprises several banks of registers (21, 22) for storing words, the switching system comprises at least one switching device (24) associated with each bank of registers and the calculation units exchange a word with a bank of registers by means of the associated switching device.

Abstract: A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Abstract: A data processing arrangement (1) comprises a first processor (PROC1) for providing successive sets of input data, a second processor (PROC2) for receiving successive sets of output data and a memory system (2) comprising a plurality of memory circuits (MEM) for storing the input and output data. According to the invention, the data processing arrangement further comprises a master controller (MCP) for setting up memory system by means of control commands (CC) associated with a set of input data and a set of output data. These control commands are received in the memory system by a control unit (MCU). When a data (Di) from the set of input data is provided by the first processor, this control unit selects, on the basis of the control commands, a first memory circuit and generates a write-address (AD_W) in said first memory circuit.

Abstract: A method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor, includes a step of planning 10 in the course of which an order and a timing of the operations are established, a step of estimating 13 a retention time specific to each variable, a step of forecasting 14 at least one instant at which each variable must be refreshed, a step of placement 15 in the course of which the variables are placed in the memory, a step of refreshing 16 in the course of which the variables are refreshed at the instants defined during the forecasting step 14. The method allows a reduction in the latency times and in the consumption of current which are related to the refreshing. It is of particular benefit in systems where the real time constraint is important, for example, video data processing systems.

Abstract: A data-processing arrangement comprises a plurality of elementary circuits such as processing circuits [PRC] and memory circuits [MEM]. The data-processing arrangement further comprises a controller [MCP]. The controller [MCP] is programmed to successively apply, in response to a task-initialization data [TID], control data [CD] to different subsets of elementary circuits. This causes the data-processing arrangement to process a block of data [DB] in accordance with a certain data-processing chain [DPC]. Each subset of elementary circuits implements a different element [E] of the data-processing chain [DPC].

Abstract: The present invention relates to a communicating data system comprising devices (11, 12, 13, 14) for routing said data that are interconnected by communication links, the data being transmitted in packets and a packet comprising a header. A transmitting part of a first routing device (12) comprises first storage means suitable for storing a value of at least one parameter from said header and for transmitting a coded value corresponding thereto, and first entropy coding compression means which are suitable for recoding the uncoded value, the recoded value being stored instead of the coded value after the latter is transmitted along a communication link (15).

Abstract: The invention relates to a method of communication between terminals and a central server, in which these terminals, whose principal function is MPEG-2 decoding, are diverted from this function, on request and after authorization, in order to partake in parallel in the common implementation of an auxiliary function under control of said server.

Abstract: A data processor comprises an arithmetic logic unit [ALU] for carrying out an arithmetic or logic operation on a first and second input data [OP1, OP2]. It further comprises a stack [STCK] for storing data and for applying a data having a certain position [P(1)] in the stack to the arithmetic logic unit [ALU] as the first input data [OP1]. The data processor can execute an instruction [INSTR] which comprises an address [ADDR] indicating a memory location [REG(i)] among a plurality of memory locations [REG]. The address [ADDR] causes a data, which is contained in the memory location [REG(i)] that it indicates, to be applied to the arithmetic logic unit [ALU] as the second input data [OP2].

Abstract: A processor comprises an arithmetic logic unit (ALU) that co-operates with a stack arrangement (STCK). The processor is arranged to execute instructions (INSTR) which include a stack control field (SCF) and an opcode field (OPF) for controlling the stack arrangement (STCK) and the arithmetic logic unit (ALU), respectively.

Abstract: A processor comprises an arithmetic logic unit (ALU) that co-operates with a stack arrangement (STCK). The processor is arranged to execute instructions (INSTR) which include a stack control field (SCF) and an opcode field (OPF) for controlling the stack arrangement (STCK) and the arithmetic logic unit (ALU), respectively.

Abstract: The invention relates to the field of digital television. It particularly relates to a device 11 for correcting geometrical faults of a cathode ray tube 10. This device comprises means 111 for adjusting spatial digital factors, these spatial digital factors controlling a digital circuit 112 for spatially processing images displayed on the screen 10. These adjusting means are controlled by control signals 16 which may be generated by a user by means of a remote control unit 12 and a control interface 113. The correction may also be automatic when the faults are due to certain characteristics of the image to be displayed, such as brilliance. In this case, measuring means 110 evaluate the brilliance of the image and generate a control signal 17 as a function of this brilliance.

Abstract: A data-processing arrangement (DPA) comprises an interrupt generator (IG). The interrupt generator (IG) carries out a count (CNT) of events (E) of a certain type (T1) occurring in the data-processing arrangement (DPA). The interrupt generator (IG) provides an interrupt signal (IS) when a predefined number (N) of events (E[T1]) have been counted. The interrupt generator (IG) comprises a programmable start-event selector (SEL[STRT]) for selecting a type (T2) of event (E) which starts (STRT) the count (CNT). Accordingly, there is no need for any controller to start the count and, consequently, there is neither need for a further interrupt generator nor for a special subroutine to make the controller start the count. Consequently, the data processing arrangement as summarized hereinbefore yields better efficiency either cost-wise or software-wise, or both.

Abstract: A data-processing arrangement (DPA) comprises an interrupt generator (IG). The interrupt generator (IG) carries out a count (CNT) of events (E) of a certain type (T1) occurring in the data-processing arrangement (DPA). The interrupt generator (IG) provides an interrupt signal (IS) when a predefined number (N) of events (E[T1]) have been counted. The interrupt generator (IG) comprises a programmable start-event selector (SEL[STRT]) for selecting a type (T2) of event (E) which starts (STRT) the count (CNT).

Abstract: A data processing device comprises a plurality of processors, for example 101, that are to access a memory system 150. The memory system 150 comprises at least two memories 111 and 112. The data processing device comprises a bus, for example 121, per memory. The buses are interconnected by at least one bridge, for example 131. A processor is connected to a bus, and the data processing device comprises at least one memory table, for example 141, specifying with which memory an exchange of a data item between a processor and the memory system 150 must be effected.