Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. In addition, the bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

Abstract: A cloud computing system includes a virtual server outputs non-encrypted data and receives encrypted data in response to receiving a write request signal and a read request signal. A hosting server hypervisor receives the write request signal and the read request signal. In response to receiving the write request signal the hosting server hypervisor writes encrypted data corresponding to the write request signal into a storage device. In response to receiving the read request signal the hosting server hypervisor obtains encrypted data corresponding to a data read request signal from the storage device and outputs the encrypted data. A secure channel sub-system is installed between the at least one virtual server and the hosting server hypervisor.

Abstract: A computer program product for optimizing page table manipulations is provided and includes a computer readable storage medium having program instructions that are readable and executable by a processing circuit to cause the processing circuit to create and maintain a translation table with a translation look-aside buffer (TLB) disposed to cache priority translations, update the translation table upon de-registration of a DMA address, allocate entries in the translation table from low to high memory addresses during memory registration, maintain a cursor for identifying where to search for available entries upon performance of a new registration, advance the cursor from entry-to-entry in the translation table and wrap the cursor from an end of the translation table to a beginning of the translation table and issue a synchronous TLB invalidation instruction to invalidate the TLB upon at least one wrapping and an entry being identified and updated.

Abstract: A method is provided for providing access to a data block in a device of a processing system. The device is connected to a processor of the processing system via an extension bus, and the processing system includes a memory connected to the processor via a memory bus, an operating system and hardware and/or firmware components for controlling access to the device. The method includes adding by the operating system for the data block a first entry in a page table of the processing system. The added entry represents the data block. A memory management unit (MMU) of the processing system may receive a request of the data block. Upon receiving the request, the MMU may instruct one of the hardware or firmware components to provide access to the data block using the added entry.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for processing a thread of execution on a plurality of independent processing cores. In various embodiments, a run state and a local maximum thermal power is assigned to each of at least part of the cores. A first one of the cores is set to the active state. The thread on the first core in the active state is processed. The processing of the thread on the first core for fulfilment of an interrupt condition is monitored. A second one of the cores is set to the active state. The processing of the thread on the first core is halted. The processing of the thread to the second core is transferred. The processing of the thread on the second core in the active state continues and the first core is set to the cooling state.

Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: The invention relates to a method for transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program and the input/output device. An operating system provides a trigger address range in a virtual address space assigned to the computer program. A page fault is caused by accessing the trigger address by the computer program. A page fault handler handling the page fault acquires information for identifying the data to be transferred using the trigger address. The acquired information is provided to the input/output device and the identified data is transferred between the memory and the input/output device.

Abstract: The present disclosure relates to methods for improving the nutritional quality of fermentation by-products derived from starch-containing material, wherein the fermentation step is carried out in the presence of a first enzyme composition comprising at least one hemicellulase, and wherein the process comprises further the steps of i) subjecting the fermented mash after the fermentation to a second enzyme composition comprising a beta-1,3 glucanase and a xylanase, ii) separating the desired fermentation product by distillation.

Abstract: A method of producing a fermentation product from starch containing material, the method including converting starch containing material to fermentable sugars, wherein the starch containing material is corn; fermenting the fermentable sugars with a microorganism into fermented mash; subjecting fermentation medium, during the fermentation process to an enzyme composition comprising a xylanase and a pectinase; and separating fermentation product from the fermented mash.

Abstract: The present technology provide a method of dewatering whole stillage. The addition of a xylanase in combination with a pectinase results in a wet cake with a higher dry mass. The advantage here is less energy consumption while drying.

Abstract: A method of recovering oil, which includes (a) converting a starch-containing material into dextrins with an alpha-amylase; (b) saccharifying the dextrins using a carbohydrate source generating enzyme to form a sugar; (c) fermenting the sugar in a fermentation medium into a fermentation product using a fermenting organism, wherein the fermentation medium comprises a xylanase and a pectinase; (d) distilling the fermentation product to form a whole stillage; (e) separating the whole stillage into thin stillage and wet cake; and (f) recovering the oil from the thin stillage.

Abstract: The present technology relates to methods of reducing the batch time in a fermentation process, wherein the fermentation medium is subjected before, during and/or after the fermentation process to an enzyme composition comprising at least a xylanase and a pectinase.