Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

Abstract: Aspects include defining a first percentage of storage areas in an array of multiple persistent storage elements as hot storage areas and a second percentage of storage areas as spare storage areas such that remaining storage areas define a third percentage as cold storage areas. Each of the storage areas are assigned to either the hot group, the spare group or the cold group, respectively. A hot and cold storage area each include a first storage block on two different storage elements, and the hot storage area and the cold storage area each include a corresponding second storage block on a storage element different to the storage element on which the first respective storage block is stored. The storage blocks are distributed across the storage elements such that blocks of storage areas with the highest write rate of all storage areas are placed on a hottest storage element.

Abstract: The present technology relates to methods of producing a fermentation product from starch containing material, wherein the fermentation medium is subjected before, during and/or after the fermentation process to an enzyme composition comprising a xylanase and a pectinase.

Abstract: The present technology relates to processes of fermenting a starch-containing material into a fermentation product comprising a fermentation step in the presence of a xylanase in combination with a pectinase on oil partitioning during post-fermentation processing. In particular, the enzyme(s) were added during simultaneous saccharification and fermentation. The finished beer was subjected to beer well incubation, distillation, and then decanting to separate thin stillage from the solids.

Abstract: A computer program product for optimizing page table manipulations is provided and includes a computer readable storage medium having program instructions that are readable and executable by a processing circuit to cause the processing circuit to create and maintain a translation table with a translation look-aside buffer (TLB) disposed to cache priority translations, update the translation table upon de-registration of a DMA address, allocate entries in the translation table from low to high memory addresses during memory registration, maintain a cursor for identifying where to search for available entries upon performance of a new registration, advance the cursor from entry-to-entry in the translation table and wrap the cursor from an end of the translation table to a beginning of the translation table and issue a synchronous TLB invalidation instruction to invalidate the TLB upon at least one wrapping and an entry being identified and updated.

Abstract: In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into one or more partitions, including at least a first partition, and providing each partition for storage as individual stored objects in an OSD system. A processor adds a first entry in a page table, the first entry representing the first partition without an indication of a physical address. A memory management unit (MMU) of the OSD system receives a first request of the first partition. Responsive to receiving the first request of the first partition, a MMU identifies that the first entry of the page table represents the first partition. A MMU obtains a physical address of the first partition from one of a hardware component and a firmware component.

Abstract: In an approach for determining a physical address for object access in an object-based storage device (OSD) system, a processor divides a first data object into one or more partitions, including at least a first partition, and providing each partition for storage as individual stored objects in an OSD system. A processor adds a first entry in a page table, the first entry representing the first partition without an indication of a physical address. A memory management unit (MMU) of the OSD system receives a first request of the first partition. Responsive to receiving the first request of the first partition, a MMU identifies that the first entry of the page table represents the first partition. A MMU obtains a physical address of the first partition from one of a hardware component and a firmware component.

Abstract: Aspects include for performing an initialization sequence by a first device to execute synchronous input/output (I/O) commands across a synchronous I/O link. The initialization sequence includes posting, by the first device, a first acknowledgement in response to a register area corresponding to a second device being updated with first information according to a first synchronization sequence, the first information comprising a worldwide node name of the second device and posting, by the first device, a second acknowledgement in response the register area being updated with second information according to a second synchronization sequence, the second information comprising mailbox information. The initialization sequence also includes performing, by the first device, a third synchronization sequence to provide a worldwide node name of the first device; and performing, by the first device, a fourth synchronization sequence to provide a status area address.

Abstract: Aspects include for performing an initialization sequence by a first device to execute synchronous input/output (I/O) commands across a synchronous I/O link. The initialization sequence includes posting, by the first device, a first acknowledgement in response to a register area corresponding to a second device being updated with first information according to a first synchronization sequence, the first information comprising a worldwide node name of the second device and posting, by the first device, a second acknowledgement in response the register area being updated with second information according to a second synchronization sequence, the second information comprising mailbox information. The initialization sequence also includes performing, by the first device, a third synchronization sequence to provide a worldwide node name of the first device; and performing, by the first device, a fourth synchronization sequence to provide a status area address.

Abstract: A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the computer system. The memory unit includes a page table and an operating system, where each data block of the data blocks is accessed via a virtual address. The method further includes: adding an entry in the page table for each data block of a first set of the data blocks, the page table represents the virtual address; checking that a first entry of the added entries represents a first virtual address, in response to receiving a request of a first data block via the first virtual address by a memory management unit of the computer system; and obtaining a first physical address of the first data block from the hardware components, and the added entry is provided without indication of the first physical address.

Abstract: A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the computer system. The memory unit includes a page table and an operating system, where each data block of the data blocks is accessed via a virtual address. The method further includes: adding an entry in the page table for each data block of a first set of the data blocks, the page table represents the virtual address; checking that a first entry of the added entries represents a first virtual address, in response to receiving a request of a first data block via the first virtual address by a memory management unit of the computer system; and obtaining a first physical address of the first data block from the hardware components, and the added entry is provided without indication of the first physical address.

Abstract: The invention relates to a method for managing virtual machine image disk usage comprising a disk image emulator for a virtual machine provided by a hypervisor, comprising the steps of providing at least a first disk image comprising a sequence of data blocks for accumulating write operations to the first disk image, providing at least a second disk image comprising a sequence of data blocks for permanently storing disk image data, and providing a disk cleaning process for transferring disk image data from the first disk image to the second disk image and deleting unused data blocks in the first and/or the second disk image.

Abstract: The invention relates to a method for managing virtual machine image disk usage comprising a disk image emulator for a virtual machine provided by a hypervisor, comprising the steps of providing at least a first disk image comprising a sequence of data blocks for accumulating write operations to the first disk image, providing at least a second disk image comprising a sequence of data blocks for permanently storing disk image data, and providing a disk cleaning process for transferring disk image data from the first disk image to the second disk image and deleting unused data blocks in the first and/or the second disk image.

Abstract: A computer system that includes a processor, a memory and a processor cache for the main memory with a check-in-cache instruction may be provided. The processor executes computer readable instructions stored in the memory that include receiving a check-in-cache instruction from a check-in-cache storage location. The instructions also include responsive to receiving the check-in-cache instruction, determining whether data bytes specified by the check-in-cache instruction are at least partially available in the processor cache. The instructions further include storing a condition code of the determination result in a storage location.

Abstract: A computer system for implicit input-output send on cache operations of a central processing unit is provided. The computer system comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit. The computer system further comprises, a memory management unit of the central processing unit, interpreting address space descriptors for implicit input-output transmittal of the input-output data of the aggregation queue.

Abstract: A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit. The method further comprises, a memory management unit of the central processing unit, interpreting address space descriptors for implicit input-output transmittal of the input-output data of the aggregation queue. The method further comprises, a cache traffic monitor of the central processing unit, transmitting the input-output data in an implicit input-output transmittal range between the cache traffic monitor and the aggregation queue, wherein the cache traffic monitor transmits cache protocol of the central processing unit to the memory management unit.

Abstract: The invention relates to a method for managing virtual machine image disk usage comprising a disk image emulator for a virtual machine provided by a hypervisor, comprising the steps of providing at least a first disk image comprising a sequence of data blocks for accumulating write operations to the first disk image, providing at least a second disk image comprising a sequence of data blocks for permanently storing disk image data, and providing a disk cleaning process for transferring disk image data from the first disk image to the second disk image and deleting unused data blocks in the first and/or the second disk image.

Abstract: An aircraft seat, including at least one electronics unit and at least one seat frame unit. The electronics unit is at least partially arranged in a hollow space spanned by the seat frame.

Abstract: The present technology relates to novel mycotoxin binder and the use in animal feed. The present disclosure relates also to the use of enzymes for improving the mycotoxin binding ability of by-products derived from a fermentative production process and to compositions comprising enzymes capable of degrading components in the fermented mash in the fermentation process.

Abstract: A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit. The method further comprises, a memory management unit of the central processing unit, interpreting address space descriptors for implicit input-output transmittal of the input-output data of the aggregation queue. The method further comprises, a cache traffic monitor of the central processing unit, transmitting the input-output data in an implicit input-output transmittal range between the cache traffic monitor and the aggregation queue, wherein the cache traffic monitor transmits cache protocol of the central processing unit to the memory management unit.