Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.

Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device include a program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage.

Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.

Abstract: The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract: A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract: Methods and apparatuses are disclosed for driving a node to one or more elevated voltages. One example apparatus includes a first driver circuit configured to drive a node to a first voltage, and a second driver circuit configured to drive the node to a pumped voltage after the node reaches a voltage threshold. The apparatus also includes a controller circuit configured to disable the first driver circuit and enable the second driver circuit responsive to the node reaching the voltage threshold.

Abstract: Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.