Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.

Abstract: Methods, systems, and devices for distribution-following access operations for a memory device are described. In an example, the described techniques may include identifying an activation of a first memory cell at a first condition of a biasing operation, and identifying an activation of a second memory cell at a second condition of the biasing operation, and determining a parameter of an access operation based at least in part on a difference between the first condition and the second condition. In some examples, the memory cells may be associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time.

Abstract: The present disclosure includes apparatuses and methods related to sensing operations in memory. An example apparatus can perform sensing operations on an array of memory cells by applying a first signal to a first portion of the array of memory cells and a second signal to a second portion of the array of memory cells.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event occurs to one of the memory cells responsive to the applied voltage ramp; stopping application of the voltage ramp after a particular amount of time subsequent to when the first switching event occurs; and determining which additional memory cells of the group experience the switching event during the particular amount of time. Those cells determined to have experienced the switching event responsive to the applied voltage ramp are sensed as storing a first data value and those cells determined to not have experienced the switching event responsive to the applied voltage ramp are sensed as storing a second data value. The group stores data according to an encoding function constrained such that each code pattern includes at least one data unit having the first data value.

Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.

Abstract: Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.

Abstract: Permutation coding for improved memory cell operations are described. An example apparatus can include an array of memory cells each programmable to a plurality of states. A controller coupled to the array is configured to determine an encoded data pattern stored by a number of groups of memory cells. Each of the number of groups comprises a set of memory cells programmed to one of a plurality of different collective state permutations each corresponding to a permutation in which the cells of the set are each programmed to a different one of the plurality of states to which they are programmable. The controller is configured to determine the encoded data pattern by, for each of the number of groups, determining the one of the plurality of different collective state permutations to which the respective set is programmed by direct comparison of threshold voltages of the cells of the set.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected.

Abstract: In an example, a first data structure can be read with a first read voltage dedicated to the first data structure. A second data structure that stores a larger quantity of data than the first data structure can be with a second read voltage that is dedicated to the second data structure. The first data structure can be with a third read voltage in response to a quantity of errors in reading the first data structure being greater than or equal to a first threshold quantity. The second data structure can be read with the third read voltage in response to a quantity of errors in reading the second data structure being greater than or equal to a second threshold quantity. The read voltages can be based on a temperature of an apparatus that includes the first and second data structures.

Abstract: Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory.

Abstract: Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a certain number bits having a first logic state prior to storing the user data in memory cells. Subsequently, reading the encoded user data may be carried out by applying a read voltage to the memory cells while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. The auto-referenced read may identify a particular switching event that correlates to a median threshold voltage value of the subset of the memory cells. Then, the auto-referenced read may determine a reference voltage that takes into account a statistical property of threshold voltage distribution of the subset of the memory cells. The auto-referenced read may identify a time duration to maintain the read voltage based on determining the reference voltage.

Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

Abstract: An apparatus has an array of memory cells and a controller coupled to the array. The controller is configured to track a sub-threshold leakage current through a number of memory cells of the array and determine a threshold voltage based on the sub-threshold leakage current.

Abstract: Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.

Abstract: A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.