Patents by Inventor Marcos Karnezos

Marcos Karnezos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7053477
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 30, 2006
    Assignee: ChipPAC, Inc.
    Inventors: Marcos Karnezos, Flynn Carson
  • Patent number: 7053476
    Abstract: A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-down flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.
    Type: Grant
    Filed: August 2, 2003
    Date of Patent: May 30, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7049691
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the upper and lower substrates are interconnected by wire bonding; and further in which at least one of the packages includes a stacked die package, or includes an additional stacked package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, in which one or both of the upper and lower packages is a stacked die package or in which one of the packages includes an additional stacked package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 23, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7045887
    Abstract: A semiconductor multi-package module has stacked first and second packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-up configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: May 16, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7034387
    Abstract: A semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 25, 2006
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Publication number: 20060019429
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Application
    Filed: August 26, 2005
    Publication date: January 26, 2006
    Applicant: ChipPAC, Inc
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Publication number: 20060012018
    Abstract: A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die.
    Type: Application
    Filed: December 23, 2004
    Publication date: January 19, 2006
    Applicant: ChipPAC, Inc.
    Inventors: Marcos Karnezos, Flynn Carson, Youngcheol Kim
  • Publication number: 20050269676
    Abstract: Adhesive/spacer structures used to adhere a first device, such as a die, or a package, to a second device such as a die, or a package, or a heat spreader, in a stacked semiconductor assembly, include a plurality of spaced-apart adhesive/spacer islands securing the first and the second devices to one another at a chosen separation. Either or both of the first and second devices can be a die; or, either or both of the devices can be a package. A package includes a die mounted onto and electrically interconnected to, a substrate, and where one package (an “upper” package) is stacked over either a lower die or a lower package, the upper package may be oriented either so that the die attach side of the upper package faces toward the lower die or lower package substrate (that is, the upper package may be inverted), or so that the die attach side of the upper package faces away from the lower die or lower package substrate.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 8, 2005
    Applicant: ChipPAC, Inc
    Inventors: Sang Lee, Jong Ju, Hyeog Kwon, Marcos Karnezos
  • Publication number: 20050269692
    Abstract: Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing the first wire-bonded die. That is, the first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 8, 2005
    Applicant: ChipPAC, Inc
    Inventors: Hyeog Kwon, Marcos Karnezos
  • Patent number: 6972481
    Abstract: A semiconductor multi-package module having stacked first and second packages, each package including a die attached to a substrate, in which the first and second substrates are interconnected by wire bonding, and wherein at least one said package comprises a stacked die package. Also, a method for making a semiconductor multi-package module, by providing a stacked die molded first package including a first package substrate, affixing a second molded package including a second substrate onto an upper surface of the first package, and forming z-interconnects between the first and second substrates.
    Type: Grant
    Filed: August 2, 2003
    Date of Patent: December 6, 2005
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 6967126
    Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: November 22, 2005
    Assignee: ChipPAC, Inc.
    Inventors: Taekeun Lee, Flynn Carson, Marcos Karnezos
  • Patent number: 6933598
    Abstract: A semiconductor multi-package module has an inverted second package stacked over a first package, in which the stacked packages are electronically interconnected by wire bonds, and in which at least one of the packages is provided with an electrical shield. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die and having a shield, affixing an upper molded package including an upper substrate in inverted orientation onto an upper surface of the lower package, and forming z-interconnects between the upper and lower substrates. Where the shield is situated above the lower package substrate, the inverted upper package is affixed onto an upper surface of the shield.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: August 23, 2005
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Publication number: 20050148113
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-down configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Application
    Filed: February 16, 2005
    Publication date: July 7, 2005
    Applicant: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Publication number: 20050133916
    Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package (such as a land grid array package) stacked over the first die, with, where necessary, provision (such as by a spacer) is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate. Also, devices such as computers and consumer electronics devices and portable or mobile devices such as mobile telecommunications devices, containing the module of the invention.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 23, 2005
    Applicant: Stats ChipPAC, Inc
    Inventor: Marcos Karnezos
  • Patent number: 6906416
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, and in which the first and second substrates are interconnected by wire bonding, and in which the first package includes a flip-chip ball grid array package having a flip-chip in a die-down configuration. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a flip-chip in a die-down configuration, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: June 14, 2005
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Publication number: 20050062149
    Abstract: A plastic ball grid array semiconductor package, employs a large heat spreader, externally attached to the upper surface of the mold cap, to provide improved thermal performance in a thin package format. The plastic ball grid array structure in the package can be constructed substantially as a standard PBGA, although in some embodiments the PBGA has a thinner molding than usual for a standard PBGA, or the wire bonding has a lower loop profile than usual, or the semiconductor device is thinner than usual. The invention can be particularly useful in applications where greater power dissipation is required, or where thin form factors and small footprints are desired.
    Type: Application
    Filed: October 13, 2004
    Publication date: March 24, 2005
    Applicant: ChipPAC, Inc
    Inventors: Marcos Karnezos, Bret Zahn, Flynn Carson
  • Patent number: 6838761
    Abstract: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming wire bond z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: August 2, 2003
    Date of Patent: January 4, 2005
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 6828220
    Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: December 7, 2004
    Assignee: ChipPAC, Inc.
    Inventors: Rajendra D. Pendse, Marcos Karnezos, Walter A. Bush, Jr.
  • Publication number: 20040195667
    Abstract: A semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.
    Type: Application
    Filed: July 14, 2003
    Publication date: October 7, 2004
    Applicant: ChipPAC, Inc
    Inventor: Marcos Karnezos
  • Publication number: 20040124518
    Abstract: A semiconductor multi-package module has an inverted second package stacked over a first package, in which the stacked packages are electronically interconnected by wire bonds, and in which at least one of the packages is provided with an electrical shield. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die and having a shield, affixing an upper molded package including an upper substrate in inverted orientation onto an upper surface of the lower package, and forming z-interconnects between the upper and lower substrates. Where the shield is situated above the lower package substrate, the inverted upper package is affixed onto an upper surface of the shield.
    Type: Application
    Filed: October 8, 2003
    Publication date: July 1, 2004
    Applicant: ChipPAC, Inc.
    Inventor: Marcos Karnezos