Patents by Inventor Marcos Karnezos

Marcos Karnezos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6323065
    Abstract: Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is adhesively attached to the ground plane, and the interconnect substrate has a complementary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package arrangement.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: November 27, 2001
    Assignee: Signetics
    Inventor: Marcos Karnezos
  • Publication number: 20010000924
    Abstract: A molded plastic package for semiconductor devices incorporating a heat sink, controlled impedance leads and separate power and ground rings is described. The lead frame of the package, separated by a dielectric layer, is attached to a metal heat sink. It has more than one ring for power and ground connections. The die itself is attached directly onto the heat sink through a window on the dielectric and provides high power dissipation. The package is molded using conventional materials and equipment.
    Type: Application
    Filed: December 14, 2000
    Publication date: May 10, 2001
    Inventors: Marcos Karnezos, S. C. Chang, Edward G. Combs, John R. Fahey
  • Patent number: 6020637
    Abstract: Disclosed is a semiconductor package arrangement. The package arrangement includes a heat spreader for dissipating heat generated within the semiconductor package arrangement. The package further includes a ground plane having a first side that is attached to the heat spreader with an electrically insulating adhesive. The ground plane has a first aperture defining a path to a surface of the heat spreader that is configured to receive a semiconductor die. An interconnect substrate is adhesively attached to the ground plane, and the interconnect substrate has a complementary second aperture over the first aperture of the ground plane. Preferably, the interconnect substrate has a plurality of metal patterns for electrically interconnecting the semiconductor die to electrical connections that are external to the semiconductor package arrangement.
    Type: Grant
    Filed: July 14, 1997
    Date of Patent: February 1, 2000
    Assignee: Signetics KP Co., Ltd.
    Inventor: Marcos Karnezos
  • Patent number: 5843808
    Abstract: A TAB Grid Array (TGA) package allows automated assembly using established manufacturing equipment similar to those used in the production of plastic ball grid Array (PBGA) package assembly. The TGA package are formed, using as starting material, a metal strip having the same critical dimensions and tooling holes as those used for a PBGA package. In this invention, the stiffener is designed to serve as a carrier throughout the assembly of the TGA package. The wire bonded TGA cavity package, including the solder balls, is first fully assembled prior to the attachment of the semiconductor die. Subsequently, the semiconductor die is attached to the stiffener, wires are bonded between the semiconductor die and the tape frame, and the entire assembly is encapsulated. The process of the present invention provides a high device assembly yield usually not achievable by the PBGA packages.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: December 1, 1998
    Assignee: ASAT, Limited
    Inventor: Marcos Karnezos
  • Patent number: 5409865
    Abstract: A TAB Grid Array (TGA) package is a package for an integrated circuit. A TGA package provides an efficient structure and method to connect a semiconductor die encapsulated in the TGA package to an external printed circuit board (PCB). The TGA package uses a tape automated bonding (TAB) technique to provide a generally flexible dielectric film bearing a pattern of conductive traces radially emanating from a die aperture to connect to an area array of pads arranged on the tape perimeter. The pads of area array of pads are connected to the TAB traces using conventional TAB inner lead bonding techniques, or alternatively, wire bonding methods, with both the semiconductor die and the TAB traces facing down towards the PCB. In one embodiment, the back of a semiconductor die and the TAB tape are attached to a stiffener via suitable bonding agents. The stiffener provides the mechanical rigidity to the package and efficiently removes the dissipated power.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: April 25, 1995
    Assignee: Advanced Semiconductor Assembly Technology
    Inventor: Marcos Karnezos
  • Patent number: 5397921
    Abstract: A TAB Grid Array (TGA) pack package for an integrated circuit. A TGA package provides an efficient structure and method to connect a semiconductor die encapsulated in the TGA package to an external printed circuit board (PCB). The TGA package uses a tape automated bonding (TAB) technique to provide a generally flexible dielectric film bearing a pattern of conductive traces radially emanating from a die aperture to connect to an area array of pads arranged on the tape perimeter. The pads of area array of pads are connected to the TAB traces using conventional TAB inner lead bonding techniques, or alternatively, wire bonding methods, with both the semiconductor die and the TAB traces facing down towards the PCB. In one embodiment, the back of a semiconductor die and the TAB tape are attached to a stiffener via suitable bonding agents. The stiffener provides the mechanical rigidity to the package and efficiently removes the dissipated power.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: March 14, 1995
    Assignee: Advanced Semiconductor Assembly Technology
    Inventor: Marcos Karnezos
  • Patent number: 5065280
    Abstract: An electronic packaging module in which the inactive sides of integrated circuit chips are held in compression against a heat spreader by an elastomer pressed thereagainst by a multilayer flexible printed circuit board. A TAB frame, which may be demountable, interconnects integrated circuit chips to a multilayer flexible printed circuit board. A backing plate is fastened to a heat spreader so that it presses against the multilayer flexible printed circuit board. Contacts are compressed against the motherboard to interconnect the multilayer flexible printed circuit board thereto. Coaxial power connectors provide power and ground connections between non-peripheral portions of the multilayer flexible printed circuit board and the motherboard.
    Type: Grant
    Filed: August 30, 1990
    Date of Patent: November 12, 1991
    Assignee: Hewlett-Packard Company
    Inventors: Marcos Karnezos, Ravindhar Kaw, Lawrence Hanlon, Farid Matta
  • Patent number: 4862490
    Abstract: A vacuum window including a support substrate provided with a window aperture, and a membrane attached to a front surface of the substrate. The membrane has a relatively thick perimeter portion attached to the support substrate, and has a window portion aligned with the window aperture. The window portion of the membrane includes a number of relatively thin pane sections separated by relatively thick, structural rib sections. The membrane material is preferably boron nitride, boron carbide, or silicon carbide.
    Type: Grant
    Filed: February 29, 1988
    Date of Patent: August 29, 1989
    Assignee: Hewlett-Packard Company
    Inventors: Marcos Karnezos, Randal S. Jones
  • Patent number: 4813129
    Abstract: An interconnect structure for electrically coupling conductive paths on two adjacent, rigid substrates, such as PC boards or IC chips. The interconnect structure includes a number of buttons formed on a first substrate, and a number of contacts formed on a second substrate. The buttons are elastically deformable, and include a resilient core made from an organic material such as polyimide, and a metallic coating formed over the core. The two substrates are compressed between mounting plates such that the buttons are pressed against the contracts to make electrical contact.
    Type: Grant
    Filed: June 19, 1987
    Date of Patent: March 21, 1989
    Assignee: Hewlett-Packard Company
    Inventor: Marcos Karnezos
  • Patent number: 4632871
    Abstract: A structure for use in an X-ray membrane (pellicle) mask is provided in which anodic bonding of layers is employed. Anodic bonding as used here provides a permanent bond between the layers, has zero thickness and provides substantial improvements in the obtained flatness of the mask by eliminating conventional glue for attachment. By applying a voltage between a layer, such as silicon, and a glass plate, and simultaneously heating both elements a permanent bond is established which is extremely flat thus providing minimum misalignment of the mask during subsequent X-ray lithography fabrication.
    Type: Grant
    Filed: February 16, 1984
    Date of Patent: December 30, 1986
    Assignee: Varian Associates, Inc.
    Inventors: Marcos Karnezos, Howard H. Nakanos, Armand P. Neukermans