Patents by Inventor Mariam Sadaka

Mariam Sadaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200331750
    Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Mariam Sadaka, Ludovic Ecarnot
  • Patent number: 10703627
    Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: July 7, 2020
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ludovic Ecarnot
  • Publication number: 20200168584
    Abstract: Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure.
    Type: Application
    Filed: February 3, 2020
    Publication date: May 28, 2020
    Applicant: Sony Semiconductor Solutions Corporation
    Inventor: Mariam Sadaka
  • Patent number: 10553562
    Abstract: Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 4, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Mariam Sadaka
  • Publication number: 20180012869
    Abstract: Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Inventor: Mariam Sadaka
  • Patent number: 9818874
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 14, 2017
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Patent number: 9728458
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 8, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20170210617
    Abstract: Methods of forming semiconductor structures comprising one or more cavities (106), which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate (100), providing a sacrificial material (110) within the one or more cavities, bonding a second substrate (120) over the a surface of the first substrate, forming one or more apertures (140) through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.
    Type: Application
    Filed: June 11, 2014
    Publication date: July 27, 2017
    Inventors: Mariam Sadaka, Ludovic Ecarnot
  • Patent number: 9716164
    Abstract: Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventor: Mariam Sadaka
  • Patent number: 9553014
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 24, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 9511996
    Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 6, 2016
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9481566
    Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 1, 2016
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Publication number: 20160268430
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Application
    Filed: May 23, 2016
    Publication date: September 15, 2016
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Patent number: 9391011
    Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 12, 2016
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Patent number: 9349865
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 24, 2016
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Publication number: 20160086974
    Abstract: Methods of fabricating a semiconductor structure include implanting ion into a second region of a strained semiconductor layer on a multi-layer substrate to amorphize a portion of crystalline semiconductor material in the second region of the strained semiconductor layer without amorphizing a first region of the strained semiconductor layer. The amorphous region is recrystallized, and elements are diffused within the semiconductor layer to enrich a concentration of the diffused elements in a portion of the second region of the strained semiconductor layer and alter a strain state therein relative to a strain state of the first region of the strained semiconductor layer. A first plurality of transistor channel structures are formed that each comprise a portion of the first region of the semiconductor layer, and a second plurality of transistor channel structures are formed that each comprise a portion of the second region of the semiconductor layer.
    Type: Application
    Filed: August 19, 2015
    Publication date: March 24, 2016
    Inventors: Mariam Sadaka, Bich-Yen Nguyen, Ionut Radu
  • Publication number: 20160087100
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 24, 2016
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Patent number: 9293448
    Abstract: Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Mariam Sadaka
  • Patent number: 9245836
    Abstract: Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: January 26, 2016
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Patent number: 9219150
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: December 22, 2015
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville