Patents by Inventor Mariam Sadaka

Mariam Sadaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8778773
    Abstract: Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 15, 2014
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Patent number: 8728863
    Abstract: Methods of forming bonded semiconductor structures include providing a substrate structure including a relatively thinner layer of material on a thicker substrate body, and forming a plurality of through wafer interconnects through the layer of material. A first semiconductor structure may be bonded over the thin layer of material, and at least one conductive feature of the first semiconductor structure may be electrically coupled with at least one of the through wafer interconnects. A transferred layer of material may be provided over the first semiconductor structure on a side thereof opposite the first substrate structure, and at least one of an electrical interconnect, an optical interconnect, and a fluidic interconnect may be formed in the transferred layer of material. A second semiconductor structure may be provided over the transferred layer of material on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: May 20, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Mariam Sadaka
  • Patent number: 8716105
    Abstract: Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: May 6, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru
  • Patent number: 8697493
    Abstract: Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: April 15, 2014
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Patent number: 8673733
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: March 18, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8637995
    Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: January 28, 2014
    Assignee: SOITEC
    Inventor: Mariam Sadaka
  • Publication number: 20140001642
    Abstract: Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: SOITEC
    Inventor: Mariam Sadaka
  • Publication number: 20140001604
    Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: SOITEC
    Inventor: Mariam Sadaka
  • Patent number: 8617925
    Abstract: Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: December 31, 2013
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bich-Yen Nguyen
  • Publication number: 20130299997
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 14, 2013
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8575001
    Abstract: Embodiments of the present invention include methods of directly bonding together semiconductor structures. In some embodiments, a cap layer may be provided at an interface between directly bonded metal features of the semiconductor structures. In some embodiments, impurities are provided within the directly bonded metal features of the semiconductor structures. Bonded semiconductor structures are formed using such methods.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 5, 2013
    Assignee: SOITEC
    Inventor: Mariam Sadaka
  • Publication number: 20130256907
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: May 22, 2013
    Publication date: October 3, 2013
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130214423
    Abstract: Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: SOITEC
    Inventor: Mariam Sadaka
  • Publication number: 20130217206
    Abstract: Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicone and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8501537
    Abstract: Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 6, 2013
    Assignees: Soitec, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Mariam Sadaka, Ionut Radu, Didier Landru, Lea Di Cioccio
  • Patent number: 8481406
    Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: July 9, 2013
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8461017
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 11, 2013
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130075868
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Publication number: 20130043600
    Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.
    Type: Application
    Filed: October 22, 2012
    Publication date: February 21, 2013
    Applicants: SOITEC
    Inventors: Soitec, Mariam Sadaka
  • Publication number: 20130037960
    Abstract: Methods of forming bonded semiconductor structures include forming through wafer interconnects through a layer of material of a first substrate structure, bonding one or more semiconductor structures over the layer of material, and electrically coupling the semiconductor structures with the through wafer interconnects. A second substrate structure may be bonded over the processed semiconductor structures on a side thereof opposite the first substrate structure. A portion of the first substrate structure then may be removed, leaving the layer of material with the through wafer interconnects therein attached to the processed semiconductor structures. At least one through wafer interconnects then may be electrically coupled to a conductive feature of another structure, after which the second substrate structure may be removed. Bonded semiconductor structures are formed using such methods.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
    Inventors: Mariam Sadaka, Bich-Yen Nguyen