Patents by Inventor Marie Denison
Marie Denison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7968936Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.Type: GrantFiled: December 31, 2007Date of Patent: June 28, 2011Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Pinghai Hao
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Publication number: 20110151634Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.Type: ApplicationFiled: February 15, 2011Publication date: June 23, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Taylor Rice Efland
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Publication number: 20110111569Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Sameer Pendharkar, Binghua Hu, Taylor Rice Efland, Sridhar Seetharaman
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Publication number: 20110108914Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Sameer Pendharkar, Binghua Hu, Taylor Rice Efland, Sridhar Seetharaman
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Patent number: 7939863Abstract: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.Type: GrantFiled: August 7, 2009Date of Patent: May 10, 2011Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Marie Denison
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Publication number: 20110076822Abstract: A semiconductor device 100 comprising source and drain regions 105, 107, and insulating region 115 and a plate structure 140. The source and drain regions are on or in a semiconductor substrate 110. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer 120 and a thick layer 122. The thick layer includes a plurality of insulating stripes 132 that are separated from each other and that extend across a length 135 between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands 143 that are directly over individual ones of the plurality of insulating stripes.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar
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Publication number: 20110074493Abstract: An integrated circuit containing a configurable dual n/p-channel 3-D resurf high voltage MOS field effect transistor (MOSFET) is disclosed. An n-channel drain is coterminous with a p-channel source in an n-well, and a p-channel drain is coterminous with an n-channel source in a p-well. A lateral drift region including n-type drift lanes and p-type drift lanes extends between the n and p wells. A resurf layer abuts the lateral drift region. The n-channel MOS gate is separate from the p-channel MOS gate. The p-channel MOS gate may be operated as a field plate in the n-channel mode, and vice versa. An n-channel MOS transistor may be integrated into the n-channel MOS source to provide an n-channel cascode transistor configuration, and similarly for a p-channel cascode configuration, to debias parasitic bipolar transistors under the MOS gates. Circuits using the MOSFET with various loads are also disclosed.Type: ApplicationFiled: September 16, 2010Publication date: March 31, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Hannes Estl
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Patent number: 7915676Abstract: The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.Type: GrantFiled: July 21, 2005Date of Patent: March 29, 2011Assignee: Infineon Technologies AGInventors: Nils Jensen, Marie Denison
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Patent number: 7893499Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.Type: GrantFiled: April 3, 2009Date of Patent: February 22, 2011Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Sameer Pendharkar, Binghua Hu, Taylor Rice Efland, Sridhar Seetharaman
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Patent number: 7888732Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.Type: GrantFiled: April 11, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Taylor Rice Efland
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Patent number: 7883973Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.Type: GrantFiled: December 16, 2008Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Seetharaman Sridar, Marie Denison, Sameer Pendharkar
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Publication number: 20100314670Abstract: An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.Type: ApplicationFiled: May 27, 2010Publication date: December 16, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar, Umamaheswari Aghoram
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Patent number: 7847351Abstract: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.Type: GrantFiled: April 11, 2008Date of Patent: December 7, 2010Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar
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Publication number: 20100264486Abstract: An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.Type: ApplicationFiled: April 20, 2009Publication date: October 21, 2010Applicant: Texas Instruments IncorporatedInventors: Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin
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Publication number: 20100252882Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.Type: ApplicationFiled: April 3, 2009Publication date: October 7, 2010Applicant: Texas Instruments IncorporatedInventors: Marie Denison, Sameer Pendharkar, Binghua Hu, Taylor Rice Efland, Sridhar Seetharaman
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Patent number: 7786507Abstract: A 2-terminal (i.e., anode, cathode) symmetrical bi-directional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bi-directional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bi-directional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.Type: GrantFiled: January 6, 2009Date of Patent: August 31, 2010Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Pinghai Hao
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Publication number: 20100200915Abstract: One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed.Type: ApplicationFiled: February 6, 2009Publication date: August 12, 2010Applicant: Texas Instruments IncorporatedInventor: Marie Denison
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Publication number: 20100171149Abstract: A 2-terminal (i.e., anode, cathode) symmetrical bidirectional semiconductor electrostatic discharge (ESD) protection device is disclosed. The symmetrical bidirectional semiconductor ESD protection device design comprises a first and second shallow wells symmetrically spaced apart from a central floating well. Respective shallow wells comprise a first and second highly doped contact implant with opposite doping types (e.g., n-type, p-type). One or more field plates, connected to the central floating well, extend laterally outward from above the central well. The device can be used as an ESD protection device at a bidirectional I/O (e.g., in parallel with a symmetrical MOS to be protected). Upon an ESD event at an input node comprising the first and second shallow wells, a coupled npn-pnp bipolar component comprising the center well, the first and second shallow wells, and the first and second contact implants, is triggered, thereby shunting current from the first to the second shallow well.Type: ApplicationFiled: January 6, 2009Publication date: July 8, 2010Applicant: Texas Instruments IncorporatedInventors: Marie Denison, Pinghai Hao
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Publication number: 20100148125Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: Texas Instruments IncorporatedInventors: Seetharaman Sridar, Marie Denison, Sameer Pendharkar
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Patent number: 7671408Abstract: A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer.Type: GrantFiled: July 9, 2008Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventor: Marie Denison