Abstract: A method for forming a partially blocking layer for an ion implantation process, which may be varied across the IC to form regions with different dopant concentrations, and regions with varying dopant concentrations in each contiguously implanted region, is disclosed. One or more temporary and/or permanent layers may form the partially blocking layer, including a combination of different materials such as polysilicon, silicon dioxide, silicon nitride, and photoresist. The partially blocking layer may be a uniform continuous sheet which transmits a uniform fraction of dopants, or a reticulated screen which transmits dopants through multiple open areas. Several partially blocking layers, each absorbing a different fraction of implanted dopants, may be formed on an IC to produce instances of a component with different performance parameters such as operation voltage, sheet resistance or gain.

Abstract: Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.

Abstract: A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.

Abstract: A vertical drain extended metal-oxide semiconductor field effect (MOSFET) transistor or a vertical double diffused metal-oxide semiconductor (VDMOS) transistor includes: a buried layer having a first conductivity type in a semiconductor backgate having a second conductivity type; an epitaxial (EPI) layer having the first conductivity type and formed above the buried layer; a deep well having the first conductivity type in the EPI layer extending down to the buried layer; at least one shallow well having the second conductivity type in the EPI layer; a shallow implant region having the first conductivity type and formed in the shallow well; a gate electrode having a lateral component extending over an edge of the shallow well and stopping at some spacing from an edge of the shallow implant and having a vertical trench field plate extending vertically into the EPI layer.

Abstract: A semiconductor device comprising source and drain regions and insulating region and a plate structure. The source and drain regions are on or in a semiconductor substrate. The insulating region is on or in the semiconductor substrate and located between the source and drain regions. The insulating region has a thin layer and a thick layer. The thick layer includes a plurality of insulating stripes that are separated from each other and that extend across a length between the source and the drain regions. The plate structure is located between the source and the drain regions, wherein the plate structure is located on the thin layer and portions of the thick layer, the plate structure having one or more conductive bands that are directly over individual ones of the plurality of insulating stripes.

Abstract: An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall.

Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.

Abstract: Integrated circuits (ICs) utilize bipolar transistors in electro-static discharge (ESD) protection circuits to shunt discharge currents during ESD events to protect the components in the ICs. Bipolar transistors are subject to non-uniform current crowding across the emitter-base junction during ESD events, which results in less protection for the IC components and degradation of the bipolar transistor. This invention comprises multiple contact islands (126) on the emitter (116) of a bipolar transistor, which act to spread current uniformly across the emitter-base junction. Also included in this invention is segmentation of the emitter diffused region to further improve current uniformity and biasing of the transistor. This invention can be combined with drift region ballasting or back-end ballasting to optimize an ESD protection circuit.

Abstract: A quasi-vertical semiconductor component in which, by variation of the layout, the process or the wiring of inner cells, a compensation for a voltage drop along a buried layer is provided in order thus to ensure a similar operating point of the individual inner cells in the well. Therefore, the disadvantages brought about by a voltage drop in the buried layer are ultimately overcome.

Abstract: The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.

Abstract: A lateral double-diffused MOS transistor (LDMOS) has a body zone and additional body regions assigned to the body zone, thereby producing a “deep body.” The deep body results in a quasi one-dimensional course of the potential lines, with the result that the dielectric strength is increased. The self-alignment between gate and channel is preserved, and parameter fluctuations are reduced.

Abstract: A quasi-vertical semiconductor component in which, by variation of the layout, the process or the wiring of inner cells, a compensation for a voltage drop along a buried layer is provided in order thus to ensure a similar operating point of the individual inner cells in the well. Therefore, the disadvantages brought about by a voltage drop in the buried layer are ultimately overcome.

Abstract: A lateral double-diffused MOS transistor (LDMOS) has a body zone and additional body regions assigned to the body zone, thereby producing a “deep body.” The deep body results in a quasi one-dimensional course of the potential lines, with the result that the dielectric strength is increased. The self-alignment between gate and channel is preserved, and parameter fluctuations are reduced.