Patents by Inventor Mariko Suzuki

Mariko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150236097
    Abstract: A semiconductor device of an embodiment includes a p-type first diamond semiconductor layer, a p-type second diamond semiconductor layer disposed on the first diamond semiconductor layer, a plurality of n-type third diamond semiconductor layers disposed on the second diamond semiconductor layer, and a first electrode disposed on the second diamond semiconductor and the third diamond semiconductor layers. The p-type second diamond semiconductor layer has a p-type impurity concentration lower than a p-type impurity concentration of the first diamond semiconductor layer and has oxygen-terminated surfaces. Each of the third diamond semiconductor layers has an oxygen-terminated surface. The first electrode forms first junctions between the first electrode and the second diamond semiconductor. The first electrode forms second junctions between the first electrode and the third diamond semiconductor layers. The first junctions and the second junctions are Schottky junctions.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 20, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko SUZUKI, Tadashi SAKAI
  • Publication number: 20150060885
    Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko SUZUKI, Tadashi SAKAI, Chiharu OTA, Kazuto TAKAO, Takashi SHINOHE
  • Publication number: 20150061824
    Abstract: An information processing device includes a collecting unit that collects biological information of a first user and a second user. The information processing device includes a specifying unit that specifies an emotion of the first user toward the second user and an emotion of the second user toward the first user using the biological information acquired by the collecting unit. The information processing device includes a determining unit that determines whether or not to provide information on the second user to the first user based on respective emotions specified by the specifying unit.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 5, 2015
    Applicant: YAHOO JAPAN CORPORATION
    Inventors: Mariko SUZUKI, Ayaka HIRANO, Chika WATANABE, Yuichi KITAJIMA, Hiroki SASAKIDO
  • Publication number: 20150061825
    Abstract: An information processing device includes a collecting unit which collects user's biological information. The information processing device includes a determining unit which determines an emotion of the user by using the biological information collected by the collecting unit. The information processing device includes an output unit which outputs in association with information representing the user and the emotion of the user determined by the determining unit to terminal devices which are used by other users.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 5, 2015
    Applicant: YAHOO JAPAN CORPORATION
    Inventors: Mariko SUZUKI, Hiroko OTA, Chiemi TAKI, Yuki UCHIDA, Hiroshi MACHIDA
  • Patent number: 8878190
    Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011>±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • Publication number: 20140284798
    Abstract: A graphene wiring has a substrate a catalyst layer on the substrate a first graphene sheet layer on the catalyst layer and a second graphene sheet layer on the first graphene layer. The second graphene layer comprises multilayer graphene sheets. The multilayer graphene sheets are intercalated with an atomic or molecular species.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki, Mariko Suzuki
  • Publication number: 20140284800
    Abstract: A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Masayuki KATAGIRI, Yuichi YAMAZAKI, Naoshi SAKUMA, Mariko SUZUKI
  • Publication number: 20140284799
    Abstract: A semiconductor device has a substrate a lower layer wiring on the substrate, an interlayer dielectric on the lower layer wiring having a contact hole, a catalyst metal layer at the bottom of the contact hole having catalyst metal particles, multi-walled carbon nanotubes on the catalyst metal layer passing through the contact hole, and an upper layer wiring on the multi-walled carbon nanotubes. The multi-walled carbon nanotubes are intercalated with an atomic or molecular species.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KATAGIRI, Tadashi SAKAI, Hisao MIYAZAKI, Yuichi YAMAZAKI, Mariko SUZUKI
  • Publication number: 20140145210
    Abstract: A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko SUZUKI, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • Publication number: 20140117548
    Abstract: A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.
    Type: Application
    Filed: July 25, 2013
    Publication date: May 1, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KATAGIRI, Yuichi YAMAZAKI, Tadashi SAKAI, Naoshi SAKUMA, Mariko SUZUKI
  • Patent number: 8710672
    Abstract: A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Katagiri, Yuichi Yamazaki, Makoto Wada, Tadashi Sakai, Naoshi Sakuma, Mariko Suzuki
  • Patent number: 8609199
    Abstract: In the growth of carbon nanotubes, the aggregation of catalytic fine particles therefor is a problem. In order to realize the growth of carbon nanotubes into a high density, the carbon nanotube growing process includes a first plasma treatment step of treating a surface having catalytic fine particles with a plasma species generated from a gas which contains at least hydrogen or a rare gas without carbon element, a second plasma treatment step of forming a carbon layer on the surface of the catalytic fine particles by a plasma generated from a gas which contains at least a hydrocarbon after the first plasma treatment step, and a carbon nanotube growing step of growing carbon nanotubes by use of a plasma generated from a gas which contains at least a hydrocarbon after the second plasma treatment step.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Mariko Suzuki, Shintaro Sato
  • Patent number: 8525399
    Abstract: According to the embodiment, an electron emission element includes a conductive substrate, a first diamond layer of a first conductivity type formed on the conductive substrate, and a second diamond layer of the first conductivity type formed on the first diamond layer. Thereby, it becomes possible to provide the electron emission element having a high electron emission amount and a high current density even in a low electric field at low temperature and the electron emission apparatus using this electron emission element.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 8497320
    Abstract: A process is provided by which a polyrotaxane including cyclic molecules having a relatively long graft chain is easily obtained. Also provided is a polyrotaxane which includes cyclic molecules having a radical polymerization initiation site and is for use as a raw material in the process. The polyrotaxane comprises: a pseudo-polyrotaxane comprising cyclic molecules clathrated with a linear molecule, the cavities of the cyclic molecules having been pierced by the linear molecule; and blocking groups disposed respectively at both ends of the pseudo-polyrotaxane so as not to release the cyclic molecules. The cyclic molecules in the polyrotaxane have a radical polymerization initiation site.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: July 30, 2013
    Assignee: Advanced Softmaterials Inc.
    Inventors: Christian Ruslim, Mariko Suzuki
  • Publication number: 20130075929
    Abstract: A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.
    Type: Application
    Filed: July 5, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Katagiri, Yuichi Yamazaki, Makoto Wada, Tadashi Sakai, Naoshi Sakuma, Mariko Suzuki
  • Publication number: 20130075757
    Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011> ±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.
    Type: Application
    Filed: July 23, 2012
    Publication date: March 28, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • Patent number: 8398927
    Abstract: A carbon nanotube manufacturing apparatus includes a plasma generating unit that generates plasma including ions, radicals, and electrons, from gas; a carbon nanotube manufacturing unit that manufactures carbon nanotubes from the radicals; a shielding electrode unit that is provided between the plasma generating unit and the carbon nanotube manufacturing unit and prevents the ions and the electrons from entering the carbon nanotube manufacturing unit; and a bias applying unit that applies a voltage to the shielding electrode unit, wherein the shielding electrode unit includes at least two first shielding electrodes that are arranged one above another, each of the first shielding electrodes having at least one opening.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Mariko Suzuki
  • Patent number: 8350160
    Abstract: A structure includes a conductive film (12) provided in an underlying layer (10); and a carbon nanotube bundle (20) including a plurality of carbon nanotubes each having one end connected to the conductive film (12), wherein, at other end side of the carbon nanotube bundle (20), at least carbon nanotubes allocated at outer side of the carbon nanotube bundle (20) extend with convex curvatures toward the outside of the carbon nanotube bundle (20), and the convex curvatures of the carbon nanotubes allocated at the outer side of the carbon nanotube bundle are larger than those of inner side of the carbon nanotube bundle (20), and diameters of the carbon nanotube bundle (20) decrease toward the other end of the carbon nanotube bundle (20).
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Mariko Suzuki
  • Patent number: 8198193
    Abstract: A manufacturing method of a semiconductor substrate includes the following steps: forming a first wiring layer on a substrate; forming an interlayer insulating film having a via hole on the wiring layer; forming carbon nanotubes in the via hole; performing a fluorination treatment entirely to the substrate; forming an embedded film in the via hole having the carbon nanotubes therein; and polishing the substrate to entirely flatten the substrate.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoshi Sakuma, Tadashi Sakai, Yuichi Yamazaki, Masayuki Katagiri, Mariko Suzuki, Makoto Wada
  • Publication number: 20120052680
    Abstract: a manufacturing method of a semiconductor substrate includes the following steps: forming a first wiring layer on a substrate; forming an interlayer insulating film having a via hole on the wiring layer; forming carbon nanotubes in the via hole; performing a fluorination treatment entirely to the substrate; forming an embedded film in the via hole having the carbon nanotubes therein; and polishing the substrate to entirely flatten the substrate.
    Type: Application
    Filed: March 7, 2011
    Publication date: March 1, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoshi SAKUMA, Tadashi Sakai, Yuichi Yamazaki, Masayuki Katagiri, Mariko Suzuki, Makoto Wada