Abstract: In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of the at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions.

Abstract: Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug.

Abstract: There is provided a catalyst and a process for converting methanol or dimethyl ether to a product containing C.sub.2 to C.sub.4 olefins. The catalyst comprises a porous crystalline material having a Diffusion Parameter for 2,2-dimethylbutane of about 0.1-20 sec.sup.-1 when measured at a temperature of 120.degree. C. and a 2,2-dimethylbutane pressure of 60 torr (8 kPa). In addition, the catalyst is characterized by a hydrothermal stability such that, after steaming the catalyst at 1025.degree. C. for 45 minutes in 1 atmosphere steam, the catalyst exhibits a methanol conversion activity of at least 50% when contacted with methanol at a methanol partial pressure of 1 atmosphere, a temperature of 430.degree. C. and 0.5 WHSV. The porous crystalline material is preferably a medium-pore zeolite, particularly ZSM-5, which contains phosphorus and has been severely steamed at a temperature of at least 950.degree. C.

Abstract: There is provided a process for converting methanol and/or dimethyl ether to a product containing C.sub.2 to C.sub.4 olefins which comprises the step of contacting a feed which contains methanol and/or dimethyl ether with a catalyst comprising a porous crystalline material, said contacting step being conducted in the presence of an aromatic compound under conversion conditions including a temperature of 350.degree. C. to 480.degree. C. and a methanol partial pressure in excess of 10 psia (70 kPa), said porous crystalline material having a pore size greater than the critical diameter of the aromatic compound and the aromatic compound being capable of alkylation by the methanol and/or dimethyl ether under said conversion conditions.

Abstract: A process is described for isomerizing a feed which contains ethylbenzene and xylene, which process comprises the steps of:(a) contacting the feed under ethylbenzene conversion conditions with a particulate first catalyst component which comprises a molecular sieve having a constraint index of 1-12, the particles of said first catalyst component having a surface to volume ratio of about 80 to less than 200 inch.sup.-1 and the contacting step converting ethylbenzene in the feed to form an ethylbenzene-depleted product; and then(b) contacting the ethylbenzene-depleted product under xylene isomerization conditions with a second catalyst component.

Abstract: A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed con

Abstract: In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions.

Abstract: The invention encompasses capacitor constructions. In one aspect, the invention includes a stacked capacitor construction comprising: a) a substrate; b) an electrically conductive runner provided on the substrate, the runner having an outer conductive surface; c) a node on the substrate adjacent the electrically conductive runner; d) an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node adjacent the conductive runner, the pillar having an outer surface; e) an electrically conductive storage node container layer in electrical connection with the pillar; f) a capacitor dielectric layer over the capacitor storage node layer; and g) an electrically conductive outer capacitor plate over the capacitor dielectric layer; and h) the pillar outer surface being elevationally inward of the runner outer surface.

Abstract: A method of fabricating capacitors for a dynamic random access memory device reduces double bit failures or shorts in the device. The method includes providing a semiconductor substrate underlying an insulative layer having a plurality of storage cells formed therein electrically connected to the substrate. A first conductive layer of rugged polysilicon, which functions as a first capacitor plate, is formed over the insulative layer in an oxygen-free atmosphere such that the first conductive layer is without natural oxides on the surface thereof. The surface of the first conductive layer in the oxygen-free atmosphere is then conditioned by a rapid thermal nitridization process which forms a silicon nitride film thereon. Thereafter, portions of the first conductive layer are removed from the insulative layer such that the plurality of storage cells are electrically isolated from one another.

Abstract: A method for forming a sidewall aligned contact structure without a hardmask layer. A semiconductor region is provided having an active area at an upper surface. An insulating layer is formed having an upper surface over the active area. Using a photo-patterned organic mask, a gross contact opening is etched in the insulating layer over the active area. The gross contact opening extends downward from the upper surface and partially through the insulating layer. A conformal layer of material is deposited at low temperature over the patterned mask as well as sidewalls and a bottom surface of the gross contact opening The conformal layer comprises a material that is differentially etchable with respect to the photomask and preferably etches similarly to the insulating layer. A portion of the insulating layer at the base of the gross contact opening is exposed. A contact opining is formed in the exposed portion of the insulating layer using the remaining conformal layer as a mask.

Abstract: A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed con

Abstract: A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed con