Patents by Inventor Mark A. Franklin

Mark A. Franklin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120311060
    Abstract: A software suite for managing the publishing and consumption of information and payload data across one or more transport protocols supported by a data-packet-network includes a posting application for publishing the information and payload data, and a consuming application for accessing and consuming the information and payload data. In a preferred embodiment the posting application enables posting of information that is consumable separately from the payload data wherein the information richly describes the payload data including provision of instructions for sampling the payload data before consuming the payload data.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Inventors: Christopher Clemmett Macleod Beck, Mark Franklin Sidell, Thomas Knox Gold, James Karl Powers, Charles Dazler Knuff
  • Patent number: 8316128
    Abstract: A software application for managing routing of communiqués across one or more communication channels supported by a data-packet-network includes one or more workspaces for segregating communication activity; one or more unique user identities assigned per workspace; and one or more contact identities assigned to and approved to communicate with a workspace administrator of the one or more workspaces using the assigned user identities. In a preferred embodiment the application enforces a policy implicitly defined by the existing architecture of the workspaces and associated user and contact identities.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: November 20, 2012
    Assignee: Forte Internet Software, Inc.
    Inventors: Christopher Clemmett Macleod Beck, Mark Franklin Sidell, Thomas Knox Gold, James Karl Powers, Charles Dazler Knuff
  • Patent number: 8250150
    Abstract: A software suite for managing the publishing and consumption of information and payload data across one or more transport protocols supported by a data-packet-network includes a posting application for publishing the information and payload data, and a consuming application for accessing and consuming the information and payload data. In a preferred embodiment the posting application enables posting of information that is consumable separately from the payload data wherein the information richly describes the payload data including provision of instructions for sampling the payload data before consuming the payload data.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: August 21, 2012
    Assignee: Forte Internet Software, Inc.
    Inventors: Christopher Clemmett Macleod Beck, Mark Franklin Sidell, Thomas Knox Gold, James Karl Powers, Charles Dazler Knuff
  • Publication number: 20120118562
    Abstract: A system, apparatus and method for abrasive jet fluid cutting is provided wherein an abrasive jet fluid cutting assembly comprises a hose for receiving a coherent abrasive jet-fluid containing a solid abrasive; a helix/spring attached inside the high-pressure hose; and a jet-nozzle connected to the hose. Wherein the coherent abrasive laden jet-fluid is pumped under high pressure through the high-pressure hose and across the helix. As the jet-fluid traverses the helix, the jet-fluid rotates at a high rate creating a vortex. The disclosed subject matter further includes a system and method for using the abrasive jet fluid cutting nozzle assembly.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 17, 2012
    Inventors: Wesley Mark McAfee, Mark Franklin Alley
  • Publication number: 20120119788
    Abstract: An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Mark Franklin Turner, Jeffrey S. Brown, Jonathan W. Byrn
  • Publication number: 20120105123
    Abstract: An apparatus for controlling clock skew in an integrated circuit (IC) includes timing circuitry operative to generate a clock signal for distribution in the IC and at least one buffer circuit operative to receive the clock signal, or a signal indicative of the clock signal, and to generate a delayed version of the clock signal as an output thereof. The buffer circuit includes at least first and second inverter stages and a resistive-capacitive (RC) loading structure. An output of the first inverter stage is connected to an input of the second inverter stage via the RC loading structure. The buffer circuit has a delay associated therewith that is selectively varied as a function of one or more adjustable characteristics of the RC loading structure. Clock skew in the IC is controlled as a function of the delay of the buffer circuit.
    Type: Application
    Filed: November 2, 2010
    Publication date: May 3, 2012
    Inventors: Jeffrey S. Brown, Mark Franklin Turner
  • Patent number: 8170882
    Abstract: Multiple channels of audio are combined either to a monophonic composite signal or to multiple channels of audio along with related auxiliary information from which multiple channels of audio are reconstructed, including improved downmixing of multiple audio channels to a monophonic audio signal or to multiple audio channels and improved decorrelation of multiple audio channels derived from a monophonic audio channel or from multiple audio channels. Aspects of the disclosed invention are usable in audio encoders, decoders, encode/decode systems, downmixers, upmixers, and decorrelators.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: May 1, 2012
    Assignee: Dolby Laboratories Licensing Corporation
    Inventor: Mark Franklin Davis
  • Publication number: 20110252008
    Abstract: Methods and apparatuses for processing data are disclosed, including methods and apparatuses that leverage a reconfigurable logic device to offload decompression and search operations from a processor to thereby enable high speed data searches within data that has been stored in a compressed format.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Inventors: Roger D. Chamberlain, Benjamin M. Brink, Jason R. White, Mark A. Franklin, Ron K. Cytron
  • Publication number: 20110209872
    Abstract: A methodology and apparatus for cutting shape(s) or profile(s) through well tubular(s), or for completely circumferentially severing through multiple tubulars, including all tubing, pipe, casing, liners, cement, other material encountered in tubular annuli. This rigless apparatus utilizes a computer-controlled, downhole robotic three-axis rotary mill to effectively generate a shape(s) or profile(s) through, or to completely sever in a 360 degree horizontal plane wells with multiple, nested strings of tubulars whether the tubulars are concentrically aligned or eccentrically aligned. This is useful for well abandonment and decommissioning where complete severance is necessitated and explosives are prohibited, or in situations requiring a precise window or other shape to be cut through a single tubular or plurality of tubulars.
    Type: Application
    Filed: September 9, 2010
    Publication date: September 1, 2011
    Inventors: Wesley Mark McAfee, Mark Franklin Alley
  • Publication number: 20110184844
    Abstract: A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a record memory is employed to store a plurality of records for a plurality of financial instruments, and a reconfigurable logic device is employed to (1) receive financial market data messages, (2) retrieve from the record memory the records for the messages' associated financial instruments, (3) process each received financial market data message to update the record for the financial instrument associated with that message, and wherein each record comprises an interest list that identifies whether any of a plurality of entities have expressed an interest in being notified of data relating to the updated record.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 28, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110179050
    Abstract: A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to (1) receive the financial market data messages, and (2) parse each received financial market data message into its constituent data fields.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110178911
    Abstract: Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110178919
    Abstract: A high speed apparatus and method for processing financial instrument order books are disclosed.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: Exegy Incorporated
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110178957
    Abstract: Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as basket calculation and volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: Exegy Incorporated
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110178912
    Abstract: A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to (1) receive the financial market data messages, and (2) process each received financial market data message to update a stored record for the financial instrument associated with that message.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110178917
    Abstract: A high speed apparatus and method for processing a plurality of financial market data messages are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to map the symbols present in the financial market data messages to another symbology.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110178918
    Abstract: A high speed system and method for processing financial instrument order data are disclosed. With respect to an exemplary embodiment, a reconfigurable logic device is employed to monitor a financial instrument order based on a risk profile to determine whether the order is appropriate. If determined appropriate, a financial instrument order can be routed to a trading venue. With respect to another exemplary embodiment, a reconfigurable logic device is employed to maintain a financial instrument order book.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 21, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Patent number: 7921046
    Abstract: Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: April 5, 2011
    Assignee: Exegy Incorporated
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Publication number: 20110040701
    Abstract: A high speed technique for options pricing in the financial industry is disclosed that can provide both high throughput and low latency. Parallel/pipelined architectures are disclosed for computing an option's theoretical fair price. Preferably these parallel/pipelined architectures are deployed in hardware, and more preferably reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) to accelerate the options pricing operations relative to conventional software-based options pricing operations.
    Type: Application
    Filed: October 26, 2010
    Publication date: February 17, 2011
    Applicant: EXEGY INCORPORATED
    Inventors: Naveen Singla, Scott Parsons, Mark A. Franklin, David E. Taylor
  • Patent number: 7871022
    Abstract: A positionable mister assembly comprises at least one nozzle structured to disperse an amount of fluid delivered from a fluid supply in the form of a mist. The positionable mister assembly includes a primary positioning portion comprising a conduit member and being structured to interconnect to a fluid supply. A secondary positioning portion is disposed in a fluid communicating relation with the primary positioning portion wherein the secondary positioning portion includes a mister supply member to which the at least one nozzle is mounted. The positionable mister assembly also includes a support portion structured to support at least the primary positioning portion in a plurality of operative orientations. In at least one embodiment the primary positioning portion, secondary positioning portion, and support portion of the positionable mister assembly are structured to be selectively interconnected to one another, allowing for a variety of configurations of the positionable mister assembly.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: January 18, 2011
    Inventor: Mark Franklin Plyler