Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

Abstract: The present disclosure is directed to microporous ladder polymers containing amine-functionalized monomer segments, amidoxime-functionalized monomer segments, or a combination thereof. Monomer compounds for preparation of the polymers are also described, as well as membranes and electrochemical cells containing the polymers.

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: The present disclosure includes apparatuses, methods, and systems for acceleration of data queries in memory. An example host apparatus includes a controller configured to generate a search key, generate a query for particular data stored in an array of memory cells in a memory device, and send the query to the memory device. The query includes a command to search for the particular data. The query also includes a number of data fields for the particular data including a logical block address (LBA) for the particular data, an LBA offset for the particular data, and a parameter for an amount of bits in data stored in the memory device that do not match corresponding bits in the search key that would result in data not being sent to the host.

Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

Abstract: A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.

Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.