Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: A processing device in a memory sub-system identifies a power loss event associated with the memory sub-system including a memory device and an ultra-high endurance storage class memory device. In response to the power loss event, the processing device further identifies a set of data corresponding to one or more in-flight operations associated with the memory device. The processing device further causes the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device. The processing device further causes execution of a data recovery operation using the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device.

Abstract: A processing device in a memory sub-system receives host data to be stored in a memory sub-system including a memory device and an ultra-high endurance storage class memory device. The processing device further causes the host data to be stored in a host data buffer of the ultra-high endurance storage class memory device. The processing device causes a first portion of the host data stored in the host data buffer to be overwritten during a buffer tenure. In response to determining that a second portion of the host data satisfied a buffer tenure requirement, causing the second portion of the host data to be written from the host data buffer to the primary memory of the memory device.

Abstract: A processing device in a memory sub-system determine that an amount of host data in a portion of an ultra-high endurance storage class memory device configured as a program buffer satisfies a buffer threshold criterion. The processing device further initiates an initial program pass of first host data from the program buffer to a portion of a memory device configured as primary memory and initiates a final program pass of the first host data from the program buffer to the primary memory.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations including programming first data to a set of memory cells of a first wordline using a first number of bits per memory cell. Responsive to receiving second data to program to the set of memory cells of the first wordline, the operations further include determining an error rate associated with a second wordline adjacent to the first wordline. Responsive to determining that the error rate satisfies a threshold criterion, the operations further include selecting a second number of bits per memory cell to program the second data to the first wordline and reprograming, using the second number of bits per memory cell, the first wordline storing the first data by programming second data to the set of memory cells while maintaining the first data.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: The present disclosure includes apparatuses, methods, and systems for acceleration of data queries in memory. An example host apparatus includes a controller configured to generate a search key, generate a query for particular data stored in an array of memory cells in a memory device, and send the query to the memory device. The query includes a command to search for the particular data. The query also includes a number of data fields for the particular data including a logical block address (LBA) for the particular data, an LBA offset for the particular data, and a parameter for an amount of bits in data stored in the memory device that do not match corresponding bits in the search key that would result in data not being sent to the host.