Patents by Inventor Mark A. Helm

Mark A. Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685702
    Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
  • Patent number: 10593624
    Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Deepak Thimmegowda, Aaron Yip, Mark Helm, Yongna Li
  • Publication number: 20200044830
    Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement contextual key management for data encryption are disclosed. Example apparatus disclosed herein to perform contextual encryption key management, which are also referred to herein as contextual key managers, include an example context discoverer to discover context information associated with a request to access first encrypted data. Such disclosed example apparatus also include an example contextual key mapper to identify a combination of context rules associated with a key that is to provide access to the first encrypted data, validate the context information associated with the request based on the combination of context rules associated with the key to determine whether the request to access the first encrypted data is valid, and obtain the key from a key management service when the request to access the first encrypted data is valid.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: Mark Ian Gargett, Shashank Visweswara, Wayne Helm Gibson, David Paul Webb
  • Publication number: 20190390269
    Abstract: The method comprises: the reverse transcription of the template RNA, the amplification and high-throughput sequencing of the cDNAs obtained in this way, the mapping of the sequenced cDNAs/reads to the reference genome using computerized alignment methods, a computerized evaluation of the mapping results with regard to the reverse transcription event pattern (the RT signature) at the nucleotide positions and feeding the digitalised data of the RT signatures into a computerized machine learning based classification system. Reverse transcription is carried out in parallel reaction batches with different reverse transcriptases and/or under different reaction conditions. The evaluation of the mapping results with regard to the RT signature is carried out using the events ‘arrest’ and/or ‘readthrough with mismatch’ and/or ‘readthrough with sequence gap(s)’. RT signature data obtained using the parallel reaction batches are fed into the classification system.
    Type: Application
    Filed: February 21, 2018
    Publication date: December 26, 2019
    Applicant: Johannes Gutenberg-Universitaet Mainz
    Inventors: Mark HELM, Ralf HAUENSCHILD, Lyudmil TSEROVSKI, Stephan WERNER, Andreas HILDEBRANDT, Jennifer LECLAIRE, Thomas KEMMER
  • Publication number: 20190378573
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Publication number: 20190369887
    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10431310
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Patent number: 10409506
    Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Publication number: 20190245796
    Abstract: A method for data rate switching in an appliance that is connected to a network includes polling data at a first rate when a value of a status of the appliance is a first value, transmitting the data polled at the first rate from the appliance via the network, polling data at a second rate when the value of the status of the appliance is a second value, and transmitting the data polled at the second rate from the appliance via the network.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Chad Michael Helms, Joseph Mark Brian
  • Publication number: 20190213073
    Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Patent number: 10289484
    Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Patent number: 10248500
    Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Publication number: 20190066771
    Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
    Type: Application
    Filed: August 28, 2017
    Publication date: February 28, 2019
    Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
  • Patent number: 10186325
    Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Mark Helm, Aaron Yip
  • Publication number: 20180373451
    Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Publication number: 20180331034
    Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Inventors: Deepak THIMMEGOWDA, Aaron YIP, Mark HELM, Yongna LI
  • Patent number: 10126967
    Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10115457
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • Publication number: 20180308551
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 25, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Patent number: 10090053
    Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Takehiro Hasegawa, Mark Helm