Patents by Inventor Mark A. Helm

Mark A. Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210200461
    Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
    Type: Application
    Filed: October 23, 2020
    Publication date: July 1, 2021
    Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
  • Patent number: 11029861
    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10891191
    Abstract: An example method for determining likelihood of erroneous data bits stored in memory cells may include sensing a first plurality of memory cells based on a first sense thresholds. Responsive to sensing the first plurality of cells, a first set of probabilistic information may be associated with the first plurality of memory cells. A second plurality of memory cells may be sensed based on a second sense threshold. Responsive to sensing the second plurality of memory cells, a second set of probabilistic information may be associated with the second plurality of memory cells. An error correction operation may be performed on the first and second pluralities of memory cells based, at least in part, on the first and second values.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Publication number: 20190378573
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 12, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Publication number: 20190369887
    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10431310
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Patent number: 10409506
    Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Publication number: 20190213073
    Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Patent number: 10289484
    Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Patent number: 10248500
    Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Publication number: 20180373451
    Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.
    Type: Application
    Filed: August 30, 2018
    Publication date: December 27, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10126967
    Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Patent number: 10115457
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • Publication number: 20180308551
    Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 25, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Patent number: 10014061
    Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory cells is selectively connected to the same data line through a respective plurality of select gates connected in series between that string and the data line. One select gate of each of the pluralities of select gates has a threshold voltage within a first range of threshold voltages, and each remaining select gate of each of the pluralities of select gates has a threshold voltage within a second range of threshold voltages mutually exclusive from the first range of threshold voltages. Each of the select gates having a threshold voltage within the first range of threshold voltages has its control gate isolated from any of the other select gates having a threshold voltage within the first range of threshold voltages.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Mark A. Helm
  • Patent number: 9947418
    Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: April 17, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Publication number: 20180081753
    Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak, Mark A. Helm, Aaron S. Yip
  • Publication number: 20170294233
    Abstract: Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of the programming pulse, and generating a subsequent programming pulse for the programming operation having the plurality of steps prior to a program voltage level of the subsequent programming pulse, wherein a particular step of the plurality of steps of the programming pulse has a different magnitude than a corresponding step of the plurality of steps of the subsequent programming pulse.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 12, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Kalyan C. Kavalipurapu
  • Publication number: 20170169885
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm
  • Patent number: 9607692
    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Qiang Tang, Feng Pan, Ramin Ghodsi, Mark A. Helm