Patents by Inventor Mark A. Helm
Mark A. Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220383949Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
-
Patent number: 11500791Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.Type: GrantFiled: December 10, 2020Date of Patent: November 15, 2022Assignee: Micron Technology, Inc.Inventors: Chulbum Kim, Mark A. Helm, Yoav Weinberg
-
Publication number: 20220357873Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
-
Publication number: 20220350517Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.Type: ApplicationFiled: June 22, 2022Publication date: November 3, 2022Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, JR., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11487436Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.Type: GrantFiled: August 17, 2020Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventors: Jeffrey S. McNeil, Jr., Niccolo' Righetti, Kishore K. Muchherla, Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11481273Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.Type: GrantFiled: August 17, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Niccolo′ Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11449271Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.Type: GrantFiled: October 23, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Mark A. Helm, Giuseppina Puzzilli, Peter Feeley, Yifen Liu, Violante Moschiano, Akira Goda, Sampath K. Ratnam
-
Publication number: 20220291865Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, JR., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11423976Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.Type: GrantFiled: June 9, 2020Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Jeremy Binfet, Mark Helm, William Filipiak, Mark Hawes
-
Patent number: 11385819Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.Type: GrantFiled: August 17, 2020Date of Patent: July 12, 2022Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Publication number: 20220215895Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.Type: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, JR., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Publication number: 20220215885Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Inventors: Mark A. Helm, Joseph T. Pawlowski
-
Publication number: 20220197771Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.Type: ApplicationFiled: March 10, 2022Publication date: June 23, 2022Inventors: Jeffrey S. McNeil, JR., Niccolo' Righetti, Kishore K. Muchherla, Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Publication number: 20220188247Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Inventors: Chulbum Kim, Mark A. Helm, Yoav Weinberg
-
Patent number: 11360700Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.Type: GrantFiled: August 17, 2020Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Publication number: 20220181341Abstract: Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.Type: ApplicationFiled: December 3, 2020Publication date: June 9, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Haitao Liu, Michael Violette, Mark A. Helm, Guangyu Huang, Vladimir Mikhalev
-
Patent number: 11309052Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.Type: GrantFiled: August 25, 2020Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Niccolo' Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11301346Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.Type: GrantFiled: August 27, 2020Date of Patent: April 12, 2022Assignee: Micron Technology, Inc.Inventors: Todd A. Marquart, Niccolo′ Righetti, Jeffrey S. McNeil, Jr., Akira Goda, Kishore K. Muchherla, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11288160Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.Type: GrantFiled: August 17, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Jeffrey S. McNeil, Jr., Niccolo′ Righetti, Kishore K. Muchherla, Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
-
Patent number: 11289166Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.Type: GrantFiled: August 4, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Mark A. Helm, Joseph T. Pawlowski