Patents by Inventor Mark A. Helm

Mark A. Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sense operation in a memory device
    Patent number: 8780626
    Abstract: Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yijie Zhao, Akira Goda, Mark A. Helm
  • METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING
    Publication number: 20140189465
    Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
    Type: Application
    Filed: December 17, 2013
    Publication date: July 3, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Uday Chandrasekhar
  • THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
    Publication number: 20140146612
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Application
    Filed: March 26, 2012
    Publication date: May 29, 2014
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Memory kink checking
    Patent number: 8711615
    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Uday Chandrasekhar, Mark A. Helm
  • MEMORY DEVICES AND OPERATING METHODS FOR A MEMORY DEVICE
    Publication number: 20140063937
    Abstract: Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Inventors: Matthew Goldman, Mark A. Helm, Jaydip B. Patel, Thomas F. Ryan
  • MEMORY PROGRAM DISTURB REDUCTION
    Publication number: 20140063960
    Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Akira Goda, Mark Helm, Pranav Kalavade, Charan Srinivasan
  • Structure and method of fabricating a transistor having a trench gate
    Patent number: 8647949
    Abstract: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 11, 2014
    Assignee: Round Rock Research, LLC
    Inventors: Michael Smith, Mark Helm, Kirk Prall
  • Methods, devices, and systems for data sensing in a memory system
    Patent number: 8631288
    Abstract: Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Uday Chandrasekhar
  • MEMORY CELL SENSING
    Publication number: 20130322170
    Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Matthew Goldman, Pranav Kalavade, Uday Chandrasekhar, Mark A. Helm
  • MEMORY KINK CHECKING
    Publication number: 20130294156
    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 7, 2013
    Inventors: Uday Chandrasekhar, Mark A. Helm
  • Reducing effects of erase disturb in a memory device
    Patent number: 8565018
    Abstract: A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
  • Non-volatile memory cell healing
    Patent number: 8542542
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, William Kueber, Mark Helm
  • Memory kink checking
    Patent number: 8482975
    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Uday Chandrasekhar, Mark Helm
  • Sense operation in a memory device
    Patent number: 8374028
    Abstract: Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: February 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Yijie Zhao, Akira Goda, Mark A. Helm
  • NON-VOLATILE MEMORY CELL HEALING
    Publication number: 20120300551
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Andrei Mihnea, William Kueber, Mark Helm
  • REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
    Publication number: 20120236640
    Abstract: A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 20, 2012
    Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
  • METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING
    Publication number: 20120240011
    Abstract: The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 20, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mark A. Helm, Uday Chandrasekhar
  • Non-volatile memory cell healing
    Patent number: 8238170
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, William Kueber, Mark Helm
  • SENSE OPERATION IN A MEMORY DEVICE
    Publication number: 20120182797
    Abstract: Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Inventors: Yijie Zhao, Akira Goda, Mark A. Helm
  • Reducing effects of erase disturb in a memory device
    Patent number: 8203876
    Abstract: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers