Patents by Inventor Mark A. Helm

Mark A. Helm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing effects of erase disturb in a memory device
    Patent number: 8203876
    Abstract: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
  • SENSE OPERATION FLAGS IN A MEMORY DEVICE
    Publication number: 20120117306
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Formation of standard voltage threshold and low voltage threshold MOSFET devices
    Patent number: 8053321
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: November 8, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Mark Helm, Xianfeng Zhou
  • REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
    Publication number: 20110128782
    Abstract: Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.
    Type: Application
    Filed: December 1, 2009
    Publication date: June 2, 2011
    Inventors: Akira Goda, Alessandro Torsi, Carlo Musilli, Mark A. Helm, Doyle Rivers
  • STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE
    Publication number: 20110124178
    Abstract: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Michael Smith, Mark Helm, Kirk Prall
  • MEMORY KINK CHECKING
    Publication number: 20110063919
    Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
    Type: Application
    Filed: September 14, 2009
    Publication date: March 17, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Uday Chandrasekhar, Mark Helm
  • Structure and method of fabricating a transistor having a trench gate
    Patent number: 7879665
    Abstract: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: February 1, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Michael Smith, Mark Helm, Kirk Prall
  • FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES
    Publication number: 20110006372
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Application
    Filed: July 12, 2010
    Publication date: January 13, 2011
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Mark Helm, Xianfeng Zhou
  • Formation of standard voltage threshold and low voltage threshold MOSFET devices
    Patent number: 7755146
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: July 13, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Mark Helm, Xianfeng Zhou
  • NON-VOLATILE MEMORY CELL HEALING
    Publication number: 20100165747
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 1, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Andrei Mihnea, William Kueber, Mark Helm
  • Non-volatile memory cell healing
    Patent number: 7701780
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, William Kueber, Mark Helm
  • Formation of standard voltage threshold and low voltage threshold MOSFET devices
    Patent number: 7696579
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: April 13, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Mark Helm, Xianfeng Zhou
  • FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES
    Publication number: 20090286366
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Application
    Filed: July 30, 2009
    Publication date: November 19, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Mark Helm, Xianfeng Zhou
  • Reduction of field edge thinning in peripheral devices
    Patent number: 7563679
    Abstract: A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as an oxidation and wet oxide etch barrier. The dielectric prevents the devices from being stripped by a wet oxide etch that can result in the exposure of the silicon corners. The exposure of a silicon corner may increase thinning of a gate oxide at the field edge. This causes variability and unreliability in the device. The dielectric is not removed from a device until the device is ready for processing. That is, the dielectric remains on a device until the growing of a gate oxide on that device has begun. This reduces the exposure of the silicon corner. Hedges that result may be removed by exposing a trench in the field oxide at the hedge.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: July 21, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Graham R. Wolstenholme, Mark A. Helm
  • Select gate transistors and methods of operating the same
    Patent number: 7554846
    Abstract: Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 30, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Mark Helm
  • Flash memory device with improved erase operation
    Patent number: 7499325
    Abstract: Some embodiments include a device having memory cells coupled to a well of a semiconductor substrate, and a select transistor coupled between the memory cells and a bit line of the device. The device may have a first circuit to raise a well voltage of the well from a first well voltage level to a second well voltage level during an erase operation. The first circuit may hold the well at the second well voltage level for a time interval during the erase operation. The device may have a second circuit to raise a voltage of the gate of the select transistor from a first gate voltage level to a second gate voltage level, which may be lower than the second well voltage level. The second circuit may hold the gate at the second gate voltage level for a time interval during the erase operation. Other embodiments including additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: March 3, 2009
    Assignee: Intel Corporation
    Inventors: Daniel H. Doyle, Mark Helm, Andrei Mihnea
  • Select gate transistors and methods of operating the same
    Publication number: 20090003061
    Abstract: Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of rows and columns, wherein each column comprises a string of the plurality of transistors coupled in series. Each such transistor includes a floating gate, a control gate, and a dielectric disposed between the floating gate and the control gate. Such a memory array also includes a plurality of select gates, wherein each select gate is coupled to each of the plurality of columns and each select gate includes a floating gate, a control gate, and an inter-gate dielectric layer. Each select gate of such a memory array also includes a switch electrically coupled between the floating gate and the control gate of the select gate and configured to switchably couple the floating gate and control gate of the select gate.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventor: Mark Helm
  • Non-volatile memory cell healing
    Publication number: 20080298123
    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Inventors: Andrei Mihnea, William Kueber, Mark Helm
  • Formation of standard voltage threshold and low voltage threshold MOSFET devices
    Patent number: 7439140
    Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
    Type: Grant
    Filed: December 4, 2006
    Date of Patent: October 21, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Mark Helm, Xianfeng Zhou
  • STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE
    Publication number: 20080200005
    Abstract: An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 21, 2008
    Inventors: Michael Smith, Mark Helm, Kirk Prall