Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Inductively coupled plasma (ICP) analyzers use an ICP torch to generate a plasma in which a sample is atomized an ionized. Analysis of the atomic ions can be performed by atomic analysis, such as mass spectrometry (MS) or atomic emission spectrometry (AES). Particle based ICP analysis includes analysis of particles such as cells, beads, or laser ablation plumes, by atomizing and ionizing particles in an ICP torch followed by atomic analysis. In mass cytometry, mass tags of particles are analyzed by mass spectrometry, such as by ICP-MS. Systems and methods of the subject application include one or more of: a demountable ICP torch holder assembly, an external ignition device; an ICP load coil comprising an annular fin, particle suspension sample introduction fluidics, and ICP analyzers thereof.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: According to a first embodiment, a feeding bottle comprises a vessel, collar, and nipple. The nipple comprises a base portion, a teat portion, an areola portion allowing movement of the teat portion towards and away from the base portion. According to a second embodiment, a feeding bottle comprises a vessel, collar, nipple and handle portion removeably secured to the vessel by the collar. The invention includes a flexible region or regions to provide a more natural feeding by closely mimicking the human breast.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: A LiDAR system includes one or more light sources configured to emit a set of light pulses in a temporal sequence with randomized temporal spacings between adjacent light pulses, one or more detectors configured to receive a set of return light pulses, and a processor configured to: determine a time of flight for each return light pulse of the set of return light pulses; and obtain a point cloud based on the times of flight of the set of return light pulses. Each point corresponds to a respective return light pulse. The processor is further configured to, for each respective point of the set of points in the point cloud: analyze spatial and temporal relationships between the respective point and a set of neighboring points in the set of points; and evaluate a quality factor for the respective point based on the spatial and temporal relationships.

Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: A LiDAR sensor includes a first lens, a first laser source configured to emit a plurality of first light pulses to be collimated by the first lens, a flood illumination source configured to emit a plurality of second light pulses as diverging light rays, a second lens configured to receive and focus (i) a portion of any one of the plurality of first light pulses and (ii) a portion of any one of the plurality of second light pulses that are reflected off of the one or more objects, a detector configured to detect (i) the portion of any one of the plurality of first light pulses and (ii) the portion of any one of the plurality of second light pulses, and a processor configured to construct a three-dimensional image of the one or more objects based on the detected portions of first light pulses and second light pulses.

Abstract: According to a first embodiment, a feeding bottle comprises a vessel, collar, and nipple. The nipple comprises a base portion, a teat portion, an areola portion allowing movement of the teat portion towards and away from the base portion. According to a second embodiment, a feeding bottle comprises a vessel, collar, nipple and handle portion removeably secured to the vessel by the collar. The invention includes a flexible region or regions to provide a more natural feeding by closely mimicking the human breast.

Abstract: Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Abstract: Sleep systems for aircraft are disclosed. An example sleep system includes a divider having a plurality of panels, each panel defining a pocket, and a lateral sleep apparatus positioned adjacent a seat, the lateral sleep apparatus to be positioned at least partially in the pocket of the panel.