Abstract: A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

Abstract: Lateral sleep systems for aircraft are disclosed. A divider is located between a first seat and a second seat of the aircraft. The divider includes a first panel oriented toward the first seat and a second panel oriented toward the second seat. The first panel defines a first support ledge. The second panel defines a second support ledge. A first lateral sleep apparatus positioned on a first side of the divider adjacent the first seat includes a first headrest and a first cradle. The first cradle supports the first headrest and includes a first panel mounting interface coupling the first headrest to the first support ledge. A second lateral sleep apparatus positioned on a second side of the divider adjacent the second seat includes a second headrest and a second cradle. The second cradle supports the second headrest and includes a second panel mounting interface coupling the second headrest to the second support ledge.

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Abstract: The invention provides for a dispenser package comprising a generally cylindrical container body and a cap removably mounted to the container body. The cap comprises a generally cylindrical cap body securable to an upper end of the container body. The cap body comprises a generally circular projecting portion having an outer circumferential surface and an upper surface that includes plural dispensing openings. A generally circular flip-up lid is connected to the cap body by a living hinge and being movable between a covering position and an open position.

Abstract: Sleep systems for aircraft are disclosed. An example sleep system includes a divider having a plurality of panels, each panel defining a pocket, and a lateral sleep apparatus positioned adjacent a seat, the lateral sleep apparatus to be positioned at least partially in the pocket of the panel.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: According to a first embodiment, a feeding bottle comprises a vessel, collar, and nipple. The nipple comprises a base portion, a teat portion, an areola portion allowing movement of the teat portion towards and away from the base portion. According to a second embodiment, a feeding bottle comprises a vessel, collar, nipple and handle portion removeably secured to the vessel by the collar. The invention includes a flexible region or regions to provide a more natural feeding by closely mimicking the human breast.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Inductively coupled plasma (ICP) analyzers use an ICP torch to generate a plasma in which a sample is atomized an ionized. Analysis of the atomic ions can be performed by atomic analysis, such as mass spectrometry (MS) or atomic emission spectrometry (AES). Particle based ICP analysis includes analysis of particles such as cells, beads, or laser ablation plumes, by atomizing and ionizing particles in an ICP torch followed by atomic analysis. In mass cytometry, mass tags of particles are analyzed by mass spectrometry, such as by ICP-MS. Systems and methods of the subject application include one or more of: a demountable ICP torch holder assembly, an external ignition device; an ICP load coil comprising an annular fin, particle suspension sample introduction fluidics, and ICP analyzers thereof.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: According to a first embodiment, a feeding bottle comprises a vessel, collar, and nipple. The nipple comprises a base portion, a teat portion, an areola portion allowing movement of the teat portion towards and away from the base portion. According to a second embodiment, a feeding bottle comprises a vessel, collar, nipple and handle portion removeably secured to the vessel by the collar. The invention includes a flexible region or regions to provide a more natural feeding by closely mimicking the human breast.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).