Abstract: A LiDAR system includes one or more light sources configured to emit a set of light pulses in a temporal sequence with randomized temporal spacings between adjacent light pulses, one or more detectors configured to receive a set of return light pulses, and a processor configured to: determine a time of flight for each return light pulse of the set of return light pulses; and obtain a point cloud based on the times of flight of the set of return light pulses. Each point corresponds to a respective return light pulse. The processor is further configured to, for each respective point of the set of points in the point cloud: analyze spatial and temporal relationships between the respective point and a set of neighboring points in the set of points; and evaluate a quality factor for the respective point based on the spatial and temporal relationships.

Abstract: According to a first embodiment, a feeding bottle comprises a vessel, collar, and nipple. The nipple comprises a base portion, a teat portion, an areola portion allowing movement of the teat portion towards and away from the base portion. According to a second embodiment, a feeding bottle comprises a vessel, collar, nipple and handle portion removeably secured to the vessel by the collar. The invention includes a flexible region or regions to provide a more natural feeding by closely mimicking the human breast.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: Sleep systems for aircraft are disclosed. An example sleep system includes a seat having a first headrest. A lateral sleep apparatus is positioned adjacent the seat. The lateral sleep apparatus includes a second headrest and a cradle coupled to the second headrest. The cradle includes a first attachment assembly and a second attachment assembly. The first attachment assembly is to couple the cradle to a support structure of a cabin of an aircraft and the second attachment assembly is to couple the cradle to the seat.

Abstract: The invention provides for a dispenser package comprising a generally cylindrical container body and a cap removably mounted to the container body. The cap comprises a generally cylindrical cap body securable to an upper end of the container body. The cap body comprises a generally circular projecting portion having an outer circumferential surface and an upper surface that includes plural dispensing openings. A generally circular flip-up lid is connected to the cap body by a living hinge and being movable between a covering position and an open position.

Abstract: Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

Abstract: Methods and apparatuses for displays are disclosed. The display includes a tray, a stand, and a biasing member. The tray comprises a plurality of walls configured to house a plurality of consumer products. The stand is coupled to the tray and comprises an interior wall disengaging an interior face of a stand edge in a first configuration in which the stand is collapsed and engaging the stand edge in a second configuration in which the stand is erect. The biasing member is coupled to the stand and biases the stand to move from the first configuration to the second configuration.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.

Abstract: A LiDAR system includes a first optical lens, and one or more first optoelectronic packages spaced apart from the first optical lens along the optical axis of the first optical lens. Each respective first optoelectronic package includes a first plurality of optoelectronic components positioned on the respective first optoelectronic package such that a surface of each respective optoelectronic component lies substantially on the first surface of best focus. The LiDAR system further includes a second optical lens, and one or more second optoelectronic packages spaced apart from the second optical lens along the optical axis of the second optical lens. Each respective second optoelectronic package includes a second plurality of optoelectronic components positioned on the respective second optoelectronic package such that a surface of each respective optoelectronic component lies substantially on the second surface of best focus.

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

Abstract: A waste storage device includes a container in which a cassette is mounted. Tubing is pulled through the centre of the cassette to store packages separated by twists. The cassette is rotated relative to the container to provide the twists between packages by virtue of a rotatable disk and user grip portion. The package is gripped against rotation by a gripper diaphragm and is guided towards a wall of the container by a guide diaphragm to prevent untwisting between packages.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

Abstract: There is disclosed in an example, a gallium nitride (GaN) field effect transistor (FET) having a gate, a drain, and a source, having: a doped GaN buffer layer; a first epitaxy layer above the buffer layer, the first epitaxy layer having a first doping profile (for example, doped, or p-type doping); and a second epitaxy layer above the first epitaxy layer, the second epitaxy layer having a second doping profile (for example, undoped, or n-type doping).