Abstract: The invention relates to a process of forming a compact bipolarjunction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if misaligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.

Abstract: The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.

Abstract: The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: Looser and tighter pitch geometries in semiconductor layouts may be fractured into separate groups and defined separately on at least two separate photomasks. Thereafter, the looser pitch geometries may be exposed using a first mask and the tighter pitch geometries may be exposed using a second mask. The conditions of exposure may be optimized for the different geometries. As a result, the customized exposures for each type of geometry may be optimized without some of the compromises conventionally required.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

Abstract: A voltage regulation module and system for an integrated circuit die. The voltage regulation module includes an interposer situated in a stack between a substrate and the integrated circuit die. The interposer includes a hybrid array of voltage regulation elements for receiving voltage from the power supply and for down-converting the voltage from the power supply into a regulated voltage supplied to the integrated circuit die. The hybrid array of voltage regulation elements includes both high-bandwidth linear regulation elements for providing voltage regulation to areas on the integrated circuit die that intermittently demand relatively high current levels, and low-bandwidth switching regulator elements that are highly power efficient.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench region features.

Abstract: An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench region features.

Abstract: An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench regions features.