Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad and the metal member and completely fills the gap. Next a second dielectric layer, having a dielectric constant greater than the first dielectric layer and being hermetic is formed over the first dielectric layer. In another embodiment of the present invention a first dielectric layer is formed on the top surface of a bond pad of a substrate. A second dielectric layer is then formed on the first dielectric. An opening is then formed through the first and second dielectric layers so as to expose the top surface of the bond pad. A barrier layer is then deposited on the sides of the opening and on the top surface of the bond pad. A contact is then formed on the barrier layer in the opening.

Abstract: The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.

Abstract: A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

Abstract: Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

Abstract: The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if mis-aligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.

Abstract: An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Abstract: The present invention discloses a method including: providing a substrate; forming a buried oxide layer over the substrate; forming a thin silicon body layer over the buried oxide layer, the thin silicon body layer having a thickness of 3-40 nanometers; forming a pad oxide layer over the thin silicon body layer; forming a silicon nitride layer over the pad oxide layer; forming a photoresist over the silicon nitride layer; forming an opening in the photoresist; removing the silicon nitride layer in the opening; partially or completely removing the pad oxide layer in the opening; removing the photoresist over the silicon nitride layer; forming a field oxide layer from the thin silicon body layer in the opening; removing the silicon nitride layer over the pad oxide layer; and removing the pad oxide layer over the thin silicon body layer.

Abstract: The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if mis-aligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.

Abstract: An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: The invention relates to a process of forming a compact bipolarjunction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.