Abstract: Graphene ink compositions comprising nitrocellulose and related methods of use comprising either thermal or photonic annealing.

Abstract: Solid-state supercapacitors and microsupercapacitors comprising printed graphene electrodes and related methods of preparation.

Abstract: Graphene ink compositions as can be utilized with gravure and screen printing processes, to provide flexible electronic components with high-resolution printed graphene circuitry.

Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.

Abstract: In one aspect of the present invention, a method for sorting nanoparticles includes preparing a high-viscosity density gradient medium filled in a container, dispersing nanoparticles into an aqueous solution to form a suspension of the nanoparticles, each nanoparticle having one or more cores and a shell encapsulating the one or more cores, layering the suspension of the nanoparticles on the top of the high-viscosity density gradient medium in the container, and centrifugating the layered suspension of the nanoparticles on the top of the high-viscosity density gradient medium in the container at a predetermined speed for a predetermined period of time to form a gradient of fractions of the nanoparticles along the container, where each fraction comprises nanoparticles in a respective one of aggregation states of the nanoparticles.

Abstract: Methods for the preparation of few-layer phosphorene, compositions thereof and related devices fabricated therefrom.

Abstract: Electrically conducting, biocompatible, biodegradable tissue growth comprising graphene flakes in a polymeric matrix are provided.

Abstract: A method of fabricating a CMOS logic device with SWCNTs includes forming a plurality of local metallic gate structures on a substrate by depositing a metal on the substrate; forming a plurality of contacts on the substrate; and depositing the SWCNTs on the substrate, and doping a certain area of the SWCNTs to form the CMOS logic device having at least one NMOS transistor and at least one PMOS transistor. Each of the NMOS and PMOS transistors has a gate formed by one of the local metallic gate structures, and a source and a drain formed by two of the contacts respectively. The gate of each PMOS transistor and the gate of each NMOS transistor are configured to alternatively receive at least one input voltage. At least one of the drain of the PMOS transistor and the drain of the NMOS transistor is configured to output an output voltage.

Abstract: A method of fabricating a diode includes forming a first semiconductor layer having a first portion and a second portion extending from the first portion on a substrate; forming first and second electrodes on the substrate, the first electrode extending over and being in contact with the first portion of the first semiconductor layer; forming an insulting film to cover the first electrode and the first portion of the first semiconductor layer; and forming a second semiconductor layer having a first portion and a second portion extending from the first portion on the substrate. The second portion of the second semiconductor layer overlapping with the second portion of the first semiconductor layer to define a vertically stacked heterojunction therewith. The first portion of the second semiconductor layer extending over and being in contact with the second electrode. Each of the first and second semiconductor layers includes an atomically thin semiconductor.

Abstract: Disclosed herein are graphene-coated lithium manganese oxide spinels cathodes for high-performance batteries Li-ion batteries and methods for making thereof. A single-layer graphene coating is shown to significantly reduce manganese loss in the cathodes while concurrently promoting the formation of a well-defined solid electrolyte interphase layer.

Abstract: The Present teachings provide, in part, methods of separating two-dimensional nanomaterials by atomic layer thickness. In certain embodiments, the present teachings provide methods of generating graphene nanomaterials having a controlled number of atomic layer(s).

Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.

Abstract: A rapid, scalable methodology for graphene dispersion and concentration with a polymer-organic solvent medium, as can be utilized without centrifugation, to enhance graphene concentration.

Abstract: Unmodified graphene oxide conjugated with hydrophilic small molecules for cellular delivery.

Abstract: In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled with the monolayer film to define a memristor channel therebetween, such that the at least one GB is located in the memristor channel, and a gate electrode capacitively coupled with the memristor channel.

Abstract: One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse.

Abstract: In one aspect of the invention, a dye sensitized solar cell has a counter-electrode including carbon-titania nanocomposite thin films made by forming a carbon-based ink; forming a titania (TiO2) solution; blade-coating a mechanical mixture of the carbon-based ink and the titania solution onto a substrate; and annealing the blade-coated substrate at a first temperature for a first period of time to obtain the carbon-based titania nanocomposite thin films. In certain embodiments, the carbon-based titania nanocomposite thin films may include solvent-exfoliated graphene titania (SEG-TiO2) nanocomposite thin films, or single walled carbon nanotube titania (SWCNT-TiO2) nanocomposite thin films.

Abstract: In one aspect of the invention, the memristor includes a monolayer film formed of an atomically thin material, where the monolayer film has at least one grain boundary (GB), a first electrode and a second electrode electrically coupled with the monolayer film to define a memristor channel therebetween, such that the at least one GB is located in the memristor channel, and a gate electrode capacitively coupled with the memristor channel.

Abstract: The Present teachings provide, in part, methods of separating two-dimensional nanomaterials by atomic layer thickness. In certain embodiments, the present teachings provide methods of generating graphene nanomaterials having a controlled number of atomic layer(s).

Abstract: In one aspect, a method of making non-covalently bonded carbon-titania nanocomposite thin films includes: forming a carbon-based ink; forming a titania (TiO2) solution; blade-coating a mechanical mixture of the carbon-based ink and the titania solution onto a substrate; and annealing the blade-coated substrate at a first temperature for a first period of time to obtain the carbon-based titania nanocomposite thin films. In certain embodiments, the carbon-based titania nanocomposite thin films may include solvent-exfoliated graphene titania (SEG-TiO2) nanocomposite thin films, or single walled carbon nanotube titania (SWCNT-TiO2) nanocomposite thin films.