Abstract: A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is provided on the layer of germanium. Incorporating germanium at the gate conductor interface with the gate oxide stabilizes the gate oxide by providing a means of drawing charge trapping sites away from the oxide.

Abstract: A semi-conductor device includes a silicon substrate. A gate oxide dielectric layer is on the silicon substrate. A gate conductor includes a relatively thin layer of germanium on the dielectric layer. A relatively thick layer of gate conductor material is provided on the layer of germanium. Incorporating germanium at the gate conductor interface with the gate oxide stabilizes the gate oxide by providing a means of drawing charge trapping sites away from the oxide.

Abstract: An improved alignment methodology for lithography. In the method, a third level is aligned to two previous levels, where the alignment mark location for the third level is calculated based upon the two previous levels in both the x- and y-directions. A preferred embodiment of the invention relates to a lithography alignment method for aligning a third level of a semiconductor device relative to first and second previous levels of the device. The method comprises the steps of forming first and second patterns at the first and second levels respectively, and determining offsets of the first and second patterns in two orthoginal directions. An optimum location for a third pattern in the third level is then determined based on an average of the offsets of the first and second patterns.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: Methods of forming merged logic DRAM devices on silicon-on-insulator (SOI) wafers having a relatively thick buried oxide region, where deep trenches are etched into the SOI substrate without etching through the buried oxide layer are provided. The methods of the present invention provide high performance SOI merged logic DRAM devices.

Abstract: A process sequence for an eight square folded bit line dynamic random access memory (DRAM) cell allows a transfer device channel length of two lithographic features. The method uses conventional processing techniques with no spacer defined features and uses conventional structures. The process sequence starts with deep trench (DT) processing, followed by deposition of insulator such as SiO2, planarization and pad strip. Then gate insulator and gate conductor are deposited. Also a pad or thin insulator can be deposited at this stage. The structure is etched using a shallow trench isolation mask and filled with SiO.sub.2. The gate conductor such as polysilicon is etched with a contact mask and reactive ion etching. If not previously deposited, a thin insulator is deposited. The structure is etched again with a gate poly contact mask. A gate conductor is then deposited. After a final etch, wiring is added.

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.

Abstract: A transfer metal configuration and fabrication process possessing increased probability of intersecting a transverse metallization level are presented, without employing an increase in actual metal thickness. The transfer metal is configured with a non-rectangular transverse cross-section such that the thickness of the electrical connect remains the same, but the transverse contact area of the exposed metal is increased. The entire transfer metal may have the same transverse cross-sectional configuration or have portions with different transverse configurations. If different configurations are employed, each portion of the transfer metal to be transversely intersected has the enhanced cross-sectional configuration. A tiered transverse configuration is presented which facilitates electrical connection of the transfer metal to a metal level on a face of a semiconductor cube structure.