Abstract: An apparatus is disclosed that includes a battery-powered wireless switch and a switch dock. The switch includes a microcontroller, a short range wireless transmitter, and one or more tactile control buttons. Additionally, the switch includes one or more docking prongs. Each docking prong is contained within a groove in a switch back, with pivot pins through one end of each docking prong perpendicular to a prong longitudinal axis and parallel to the switch back. The switch also includes flexible strips coupled to the same end of each docking prong as the pivot pins, and a prong extender button coupled to the flexible strips. The dock includes one or more docking prong slots, where the number of slots matches the number of prongs. The prongs fit in the slots to mount the switch to the dock.

Abstract: A redundant star network and methods for communicating over the network are disclosed. The network includes a peripheral device, a first network hub, and a second network hub. Each of the peripheral device, the first network hub, and the second network hub includes a wireless long range transceiver and at least one microcontroller. The first and second network hub microcontrollers store system operation information that includes instructions for operating the peripheral device and instructions for designating a peripheral device control hub. Additionally, the first and second network hub microcontrollers each include firmware for testing whether the other hub is operational and updating the system operation information to change the peripheral device control hub if it is non-operational. In some embodiments, the network is connected to a cloud server that communicates system updates to a user device.

Abstract: A redundant star network is disclosed. The network includes a peripheral device (PD), a control hub, and a backup hub. The control hub and backup hub each have a wireless long range transceiver, hardware processors, and hardware memory. The PD includes a wireless long range transceiver and a microcontroller. The control hub and backup hub hardware memories store system operation information. The system operation information includes instructions for controlling the PD. The PD microcontroller includes test firmware and update firmware. The test firmware instructs the PD to test the control hub and to listen for a test response signal indicating the control hub is operational. The PD update firmware instructs the PD to switch control of the PD to the backup hub when the test response signal is not received within an expected response timeframe after the test signal is sent.

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Abstract: A system for efficient hub switching of mobile network devices is disclosed. The system includes a peripheral device (PD), a first control hub, and a second control hub. The PD includes a wireless long range transceiver and a microcontroller, and is controlled wirelessly by the first control hub. The first control hub and second network hub each have a wireless long range transceiver, hardware processors, and hardware memory that stores system operation information. The system operation information includes instructions for controlling the PD. Additionally, the system operation information includes instructions for listening for a response from the PD. The listening instructions include an expected response timeframe after the control instructions are sent. The system operation information further includes instructions for requesting the second control hub control the PD. Furthermore, the system operation information includes instructions for taking over control of the PD.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.

Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.