Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

Abstract: A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Abstract: Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Abstract: A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

Abstract: A method for automatically allocating the time of an individual to a project is disclosed. Such a method includes associating a project with a location, such as the location of an asset, and tracking proximity of an individual to the location. A “project” may include work associated with a particular client, work order, assignment, or the like. A “location” may include a stationary or changing location. The method further determines an amount of time that the individual is deemed to be proximate the location. The method automatically allocates time of the individual to the project during the time the individual is proximate the location. In certain embodiments, the method further enables the individual to manually adjust the time that is allocated to the project during the time the individual is proximate the location. A corresponding system and computer program product are also disclosed.

Abstract: A method for automatically allocating the time of an asset is disclosed. Such a method includes tracking proximity of a first asset relative to a second asset. The first asset may include, for example, a work order or one or more individuals. The second asset may include, for example, a piece of equipment, a room, or a work area. The method determines a duration of time the first asset is deemed to be proximate the second asset. In accordance with the duration of time, the method automatically allocates time of the second assert to at least one of the first asset, an entity associated with the first asset, and a project associated with the first asset. A corresponding system and computer program product are also disclosed herein.

Abstract: A method for automatically allocating use of an asset is disclosed. Such a method includes tracking proximity of a first asset relative to a second asset and determining when the first asset is proximate the second asset. The method further senses use of the second asset while the first asset is proximate the second asset. Sensing use may include sensing vibration of the second asset, temperature of the second asset, electrical current drawn by the second asset, or the like. The method automatically allocates use of the second assert to at least one of the first asset, an entity associated with the first asset, and a project associated with the first asset. A corresponding system and computer program product are also disclosed herein.

Abstract: Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.

Abstract: A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

Abstract: A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a first layer of a material that can be used as a gate or a dummy gate. An opening is formed in the first layer in the NVM region. The opening is filled with a charge storage layer and a control gate. A select gate, which may be formed from the first layer or from a metal layer, is formed adjacent to the control gate. If it is a metal from a metal layer, the first layer is used to form a dummy gate. A metal logic gate is formed in the logic region by replacing a dummy gate.

Abstract: An oxide-containing layer is formed directly on a semiconductor layer in an NVM region, and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-k dielectric layer is formed directly on the semiconductor layer in a logic region. A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.