Patents by Inventor Mark D. Hall

Mark D. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of making semiconductor devices with non-volatile memory cells
    Patent number: 9087862
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: July 21, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic
    Patent number: 9087913
    Abstract: A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 21, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff, Frank K. Baker, Jr.
  • Non-volatile memory (NVM) and logic integration
    Patent number: 8951863
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Applications for nanopillar structures
    Patent number: 8951892
    Abstract: A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • METHODS OF MAKING MULTI-STATE NON-VOLATILE MEMORY CELLS
    Publication number: 20150037958
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: MARK D. HALL, MEHUL D. SHROFF
  • SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN SEMICONDUCTOR DEVICES
    Publication number: 20150015306
    Abstract: A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 15, 2015
    Inventors: Anis M. Jarrar, Mark D. Hall, David R. Tipple, Surya Veeraraghavan
  • Capacitive sensor radiation measurement
    Patent number: 8933711
    Abstract: A system that includes at least one capacitive sensor for least one angle of incidence component of radiation being measured striking the sensor. The measured capacitance of the sensor is affected by radiation striking the sensor. In some embodiments, the system includes multiple sensors where differences in the capacitive measurements of the sensors can be used to determine information about the radiation such as e.g. horizontal angle, directional angle, and dose.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Non-volatile memory (NVM) and logic integration
    Patent number: 8906764
    Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: December 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mehul D. Shroff, Mark D. Hall
  • Incident capacitive sensor
    Patent number: 8884241
    Abstract: A capacitive sensor device for measuring radiation. The device includes two sensor regions and top plate structure. The sensor regions are of a material that generates electron-hole pairs when radiation strikes the material. A separation region is located between the two sensor regions. The capacitance between a sensor region and top plate is dependent upon radiation striking the sensor region. A blocking structure selectively and differentially blocks radiation having a parameter value in a range from the sensor region so as to differentially impact electron-hole pair generation of one sensor region with respect to electron-hole pair generation of the other sensor region at selected angles of incidence of the radiation.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Automobile exterior
    Patent number: D718666
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 2, 2014
    Assignee: Chrysler Group LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, John S Owens, Mark D Hall, Brandon L Faurote
  • Vehicle hood
    Patent number: D718686
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: December 2, 2014
    Assignee: Chrysler Group LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, Mark D Hall, Brandon L Faurote
  • Vehicle side mirror
    Patent number: D720669
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: January 6, 2015
    Assignee: Chrysler Group LLC
    Inventors: Mohamad J Hammoud, Mark D Hall, Brandon L Faurote
  • Vehicle grille insert
    Patent number: D730785
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 2, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, Mark D Hall, Brandon L Faurote
  • Vehicle rear bumper
    Patent number: D730789
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 2, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Mark D Hall, Brandon L Faurote
  • Vehicle rear bumper
    Patent number: D730790
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 2, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Mark D Hall, Brandon L Faurote
  • Vehicle front bumper
    Patent number: D730791
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 2, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, Mark D Hall, Brandon L Faurote
  • Vehicle rear decklid
    Patent number: D731942
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: June 16, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Mark D Hall, Brandon L Faurote
  • Automobile exterior
    Patent number: D733616
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: July 7, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, John S Owens, Mark D Hall, Brandon L. Faurote
  • Vehicle grille insert
    Patent number: D736122
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 11, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, John S Owens, Mark D Hall, Brandon L Faurote
  • Vehicle grille insert
    Patent number: D736123
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 11, 2015
    Assignee: FCA US LLC
    Inventors: Mohamad J Hammoud, Jeffrey R Aneiros, Mark D Hall, Brandon L Faurote