Patents by Inventor Mark Durlam

Mark Durlam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7747926
    Abstract: A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: June 29, 2010
    Assignee: Everspin Technologies, Inc.
    Inventors: Loren J. Wise, Thomas W. Andre, Mark A. Durlam, Eric J. Salter
  • Patent number: 7511990
    Abstract: An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: March 31, 2009
    Assignee: EverSpin Technologies, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam
  • Patent number: 7510883
    Abstract: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: March 31, 2009
    Assignee: EverSpin Technologies, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam
  • Patent number: 7476329
    Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: January 13, 2009
    Assignee: EverSpin Technologies, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
  • Patent number: 7432150
    Abstract: A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: October 7, 2008
    Assignee: EverSpin Technologies, Inc.
    Inventors: Mark A. Durlam, Gloria J. Kerszykowski, Nicholas D. Rizzo, Eric J. Salter, Loren J. Wise
  • Publication number: 20080112214
    Abstract: A method and assembly for sensing a voltage with a memory cell (88) is provided. The memory cell includes first and second electrodes (96,112), first and second ferromagnetic bodies (104,108) positioned between the first and second electrodes and an insulating body (94) positioned between the first and second ferromagnetic bodies. The first electrode is electrically connected to a first portion of a microelectronic assembly (47). The second electrode is electrically connected to a second portion of the microelectronic assembly. The voltage across the first and second portions of the microelectronic assembly is determined based on an electrical resistance of the memory cell. The memory cell may be a magnetoresistive random access memory (MRAM) cell. In one embodiment, the memory cell is a magnetic tunnel junction (MTJ) memory cell.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 15, 2008
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam, Pon Sung Ku
  • Patent number: 7324369
    Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: January 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam, Gregory W. Grynkewich, Eric J. Salter
  • Publication number: 20070260962
    Abstract: A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
    Type: Application
    Filed: May 2, 2006
    Publication date: November 8, 2007
    Inventors: Loren Wise, Thomas Andre, Mark Durlam, Eric Salter
  • Patent number: 7279341
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 9, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas V. Meixner, Gregory W. Grynkewich, Jaynal A. Molla, J. Jack Ren, Richard G. Williams, Brian R. Butcher, Mark A. Durlam
  • Patent number: 7271011
    Abstract: Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: September 18, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam
  • Patent number: 7264985
    Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 4, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam, Gregory W. Grynkewich, Eric J. Salter
  • Patent number: 7262069
    Abstract: An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and at least one inductance element formed on the same substrate using the same fabrication process technology. The inductance element, which may be an inductor or a transformer, is formed at the same metal layer (or layers) as the program lines of the MRAM architecture. Any available metal layer in addition to the program line layers can be added to the inductance element to enhance its efficiency. The concurrent fabrication of the MRAM architecture and the inductance element facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: August 28, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam, Bradley N. Engel
  • Publication number: 20070190669
    Abstract: A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.
    Type: Application
    Filed: February 10, 2006
    Publication date: August 16, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mark Durlam, Gloria Kerszykowski, Nicholas Rizzo, Eric Salter, Loren Wise
  • Patent number: 7239543
    Abstract: An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 3, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Young Sir Chung, Robert W. Baird, Mark A. Durlam, Gregory W. Grynkewich, Eric J. Salter, Jiang-Kai Zuo
  • Publication number: 20070097732
    Abstract: An integrated circuit device is provided which includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may comprise a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Young Chung, Robert Baird, Mark Durlam, Gregory Grynkewich, Eric salter, Jiang-Kai Zuo
  • Publication number: 20070099308
    Abstract: Techniques are provided for sensing a first current produced by an active circuit component. According to these techniques, a current sensor is disposed over the active circuit component. The current sensor includes a Magnetic Tunnel Junction (“MTJ”) core disposed between a first conductive layer and a second conductive layer. The MTJ core can be used to sense the first current and produce a second current based on the first current sensed at the MTJ core.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 3, 2007
    Inventors: Young Chung, Robert Baird, Mark Durlam
  • Publication number: 20070077664
    Abstract: Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Young Chung, Robert Baird, Mark Durlam
  • Publication number: 20070076330
    Abstract: An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Young Chung, Robert Baird, Mark Durlam
  • Publication number: 20070045759
    Abstract: An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 1, 2007
    Inventors: Young Chung, Robert Baird, Mark Durlam, Gregory Grynkewich, Eric Salter
  • Patent number: 7169622
    Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: January 30, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Clarence J. Tracy