Patents by Inventor Mark Durlam
Mark Durlam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6903964Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.Type: GrantFiled: June 28, 2002Date of Patent: June 7, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Bradley J. Garni, Mark A. Durlam
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Patent number: 6890770Abstract: A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.Type: GrantFiled: July 6, 2004Date of Patent: May 10, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Gregory W. Grynkewich, Mark Deherrera, Mark A. Durlam, Clarence J. Tracy
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Patent number: 6888743Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.Type: GrantFiled: December 27, 2002Date of Patent: May 3, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Thomas W. Andre, Brian R. Butcher, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Gregory W. Grynkewich, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani, Clarance J. Tracy
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Patent number: 6885074Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).Type: GrantFiled: November 27, 2002Date of Patent: April 26, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
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Patent number: 6881351Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.Type: GrantFiled: April 22, 2003Date of Patent: April 19, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
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Publication number: 20050009212Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.Type: ApplicationFiled: August 5, 2004Publication date: January 13, 2005Inventors: Gregory Grynkewich, Brian Butcher, Mark Durlam, Clarence Tracy
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Patent number: 6835423Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties.Type: GrantFiled: January 22, 2003Date of Patent: December 28, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Eugene Youjun Chen, Mark Durlam, Saied N. Tehrani, Mark DeHerrera, Gloria Kerszykowski, Kelly Wayne Kyler
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Publication number: 20040257902Abstract: A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.Type: ApplicationFiled: July 6, 2004Publication date: December 23, 2004Inventors: Gregory W. Grynkewich, Mark Deherrera, Mark A. Durlam, Clarence J. Tracy
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Patent number: 6812040Abstract: A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.Type: GrantFiled: March 12, 2002Date of Patent: November 2, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Kelly Kyler, Saied N. Tehrani, John J. D'urso, Gregory W. Grynkewich, Mark A. Durlam, Brian Butcher
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Publication number: 20040211749Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.Type: ApplicationFiled: April 22, 2003Publication date: October 28, 2004Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Charles A. Synder, Kenneth H. Smith, Clarence J. Tracy, Richard Williams
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Publication number: 20040205958Abstract: A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.Type: ApplicationFiled: April 16, 2003Publication date: October 21, 2004Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Kelly Kyler, Kenneth H. Smith, Clarence J. Tracy
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Publication number: 20040197579Abstract: An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) and the second electrode (18) include ferromagnetic layers (26 & 28). A spacer layer (16) is located between the ferromagnetic layer (26) of the first electrode (14) and the ferromagnetic layer (28) of the second electrode (16) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (26 & 28). The device includes insulative veils (34) characterized as electrically isolating the first electrode (14) and the second electrode (18), the insulative veils (34) including non-magnetic and insulating dielectric properties.Type: ApplicationFiled: April 21, 2004Publication date: October 7, 2004Inventors: Eugene Youjun Chen, Mark Durlam, Saied N. Tehrani, Mark DeHerrera, Gloria Kerszykowski, Kelly Wayne Kyler
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Patent number: 6798004Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.Type: GrantFiled: April 22, 2003Date of Patent: September 28, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Gregory W. Grynkewich, Brian R. Butcher, Mark A. Durlam, Clarence J. Tracy
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Patent number: 6784510Abstract: A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.Type: GrantFiled: April 16, 2003Date of Patent: August 31, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Gregory W. Grynkewich, Mark Deherrera, Mark A. Durlam, Clarence J. Tracy
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Patent number: 6760266Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.Type: GrantFiled: June 28, 2002Date of Patent: July 6, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Bradley J. Garni, Mark F. Deherrera, Mark A. Durlam, Bradley N. Engel, Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian
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Publication number: 20040125646Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.Type: ApplicationFiled: December 27, 2002Publication date: July 1, 2004Inventors: Mark A. Durlam, Thomas W. Andre, Brian R. Butcher, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Gregory W. Grynkewich, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani, Clarance J. Tracy
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Publication number: 20040125649Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.Type: ApplicationFiled: October 2, 2003Publication date: July 1, 2004Inventors: Mark A. Durlam, Thomas W. Andre, Mark F. Deherrera, Bradley N. Engel, Bradley J. Garni, Joseph J. Nahas, Nicholas D. Rizzo, Saied Tehrani
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Publication number: 20040099908Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
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Publication number: 20040001383Abstract: A sense amplifier (1300, 1500) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier (1300, 1500) employs a sample-and-hold circuit (1336, 1508) combined with a current-to-voltage converter (1301, 1501), gain circuit (1303), and cross-coupled latch (1305, 1503) to sense the state of a bit. The sense amplifier (1300, 1500), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier (1300, 1500) compares the first state to the second state to determine the first state of a toggling type memory cell.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: Bradley J. Garni, Mark F. Deherrera, Mark A. Durlam, Bradley N. Engel, Thomas W. Andre, Joseph J. Nahas, Chitra K. Subramanian
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Publication number: 20040001358Abstract: A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: Joseph J. Nahas, Thomas W. Andre, Chitra K. Subramanian, Bradley J. Garni, Mark A. Durlam