Patents by Inventor Mark E. Tuttle

Mark E. Tuttle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11020811
    Abstract: A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Publication number: 20210091037
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 25, 2021
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Publication number: 20210074671
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Patent number: 10943842
    Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle
  • Publication number: 20210059074
    Abstract: A semiconductor device includes functional circuits electrically coupled to each other and each coupled to a different thermal circuit. The different thermal circuits are configured to maintain different operating temperatures targeted for each corresponding functional circuit. One of the thermal circuits may use a cryogenic liquid to cool the corresponding functional circuit.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 25, 2021
    Inventor: Mark E. Tuttle
  • Publication number: 20200409438
    Abstract: An apparatus comprising a relatively high temperature electronic device, a relatively low temperature electronic device operably coupled to the relatively high temperature electronic device. The operable coupling comprises at least one of optical coupling, inductive coupling or capacitive coupling through at least one contained free space located between the electronic device and the other electronic device across one of air or a full or partial vacuum in a volume of the contained free space adjacent a path of the operable coupling. Related systems and methods are also disclosed.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Inventor: Mark E. Tuttle
  • Publication number: 20200395337
    Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: Owen R. Fay, Chan H. Yoo, Mark E. Tuttle
  • Patent number: 10840210
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Patent number: 10840209
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Patent number: 10834853
    Abstract: A semiconductor device includes a substrate; a first functional circuit attached to the substrate; a first thermal circuit attached to the substrate, configured to utilize cryogenic liquid to cool the first functional circuit; a second functional circuit attached to the substrate; and a second thermal circuit attached to the substrate, configured to cool the second functional circuit without using the cryogenic liquid.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Publication number: 20200321317
    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20200258859
    Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: Mark E. Tuttle, John F. Kaeding, Owen R. Fay, Eiichi Nakano, Shijian Luo
  • Patent number: 10712382
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 10714456
    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20200211999
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Publication number: 20200212000
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Publication number: 20200211996
    Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Patent number: 10692793
    Abstract: A semiconductor device includes a substrate; a die attached to the substrate; an encapsulation covering the substrate and the die, wherein the die is embedded within the encapsulation; and a heating element embedded within the encapsulation, wherein the heating element is configured to provide thermal energy to the die.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Publication number: 20200168517
    Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle
  • Publication number: 20200126907
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 23, 2020
    Inventors: Eiichi Nakano, Mark E. Tuttle