Patents by Inventor Mark G. Johnson

Mark G. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090173985
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 9, 2009
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Peti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald
  • Patent number: 7383476
    Abstract: In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: June 3, 2008
    Assignee: SanDisk 3D LLC
    Inventors: Matthew P. Crowley, Luca G. Fasoli, Alper Ilkbahar, Mark G. Johnson, Bendik Kleveland, Thomas H. Lee, Roy E. Scheuerlein
  • Patent number: 7308065
    Abstract: A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: December 11, 2007
    Assignee: Rambus Inc.
    Inventors: Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson, Benedict C. Lau, Leung Yu, Bruno W. Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Vi Tran, Donald C. Stark, Nhat M. Nguyen
  • Patent number: 7283403
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: October 16, 2007
    Assignee: SanDisk 3D LLC
    Inventor: Mark G. Johnson
  • Patent number: 7236023
    Abstract: Apparatus and methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature, without requiring an externally-supplied reference signal.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: June 26, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Tyler J. Thorp, Mark G. Johnson, Brent Haukness
  • Patent number: 7203084
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: April 10, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Mark G. Johnson
  • Patent number: 7190602
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: March 13, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, Thomas H. Lee, James M. Cleeves
  • Patent number: 7177183
    Abstract: Extremely dense memory cell structures provide for new array structures useful for implementing memory and logic functions. An exemplary non-volatile memory array includes a first plurality of X-lines configured to be logically identical in a read mode of operation, and each associated with a first Y-line group numbering at least one Y-line. Each of the first plurality of X-lines may also be associated with a second Y-line group numbering at least one Y-line. In some embodiments, the first and second Y-Line groups are simultaneously selectable in a read mode and, when so selected, are respectively coupled to true and complement inputs of a sense amplifier circuit. Such Y-line groups may number only one Y-line, or may number more than one Y-line. Many types of memory cells may be used, such as various passive element cells and EEPROM cells, in both 2D or 3D memory arrays.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 13, 2007
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Luca Fasoli, Mark G. Johnson
  • Patent number: 7129538
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: October 31, 2006
    Assignee: Sandisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul M. Farmwald, Brad Herner
  • Patent number: 7039147
    Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 2, 2006
    Assignee: Rambus Inc.
    Inventors: Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson, Benedict C. Lau, Leung Yu, Bruno W. Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Vi Tran, Donald C. Stark, Nhat M. Nguyen
  • Patent number: 6996017
    Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 7, 2006
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roy E. Scheuerlein, Mark G. Johnson, Derek J. Bosch, Alper Ilkbahar, J. James Tringali
  • Patent number: 6954394
    Abstract: The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: October 11, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: N. Johan Knall, Roy E. Scheuerlein, James M. Cleeves, Bendik Kleveland, Mark G. Johnson
  • Patent number: 6901549
    Abstract: The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: May 31, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roger W. March, Christopher S. Moore, Mark G. Johnson
  • Patent number: 6888750
    Abstract: A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: May 3, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Andrew J. Walker, Mark G. Johnson, N. Johan Knall, Igor G. Kouznetsov, Christopher J. Petti
  • Patent number: 6881994
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: April 19, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner
  • Patent number: 6867992
    Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: March 15, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: J. James Tringali, P. Michael Farmwald, Thomas H. Lee, Mark G. Johnson, Derek J. Bosch
  • Patent number: 6868022
    Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: March 15, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Roy E. Scheuerlein, Mark G. Johnson, Derek J. Bosch, Alper Ilkbahar, J. James Tringali
  • Publication number: 20040250183
    Abstract: This invention is directed to a chip-level architecture used in combination with a monolithic three-dimensional write-once memory array.
    Type: Application
    Filed: February 9, 2004
    Publication date: December 9, 2004
    Inventors: Matthew P. Crowley, Luca G. Fasoli, Alper Ilkbahar, Mark G. Johnson, Bendik Kleveland, Thomas H. Lee, Roy E. Scheuerlein
  • Publication number: 20040223571
    Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.
    Type: Application
    Filed: February 14, 2003
    Publication date: November 11, 2004
    Applicant: Rambus Inc.
    Inventors: Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson, Benedict C. Lau, Leung Yu, Bruno W. Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Vi Tran, Donald C. Stark, Nhat M. Nguyen
  • Publication number: 20040206982
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: May 6, 2004
    Publication date: October 21, 2004
    Inventors: Thomas H. Lee, Mark G. Johnson