Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: This invention is directed to a chip-level architecture used in combination with a monolithic three-dimensional write-once memory array.

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: The preferred embodiments described herein relate to a redundant memory structure using bad bit pointers. In one preferred embodiment, data is written in a first plurality of memory cells, and an error is detected in writing data in one of the memory cells. In response to the detected error, a pointer is written in a second plurality of memory cells, the pointer identifying which memory cell in the first plurality of memory cells contains the error. During a read operation, the data is read from the first plurality of memory cells, and the pointer is read from the second plurality of memory cells. From the pointer, the memory cell containing the error is identified, and the error is corrected. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Abstract: The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Abstract: Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.

Abstract: An integrated circuit includes a serially-connected, multi-level, mask-programmed read-only memory array. The memory cells are preferably programmed using selective ion implantation of at least two threshold-adjusting ion implants during the manufacture of the integrated circuit to store more than one bit of information within each memory cell, which are chosen to generate an evenly spaced set of different transistor threshold voltages.

Abstract: A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.

Abstract: A 3-dimensional read only memory includes vertically stacked layers of memory cells. Each of the memory cells includes a mask programmed insulating layer, a pair of diode components, and a pair of crossing-conductors. The conductors (other than those at the top and the bottom of the array) each connect to both overlying conductors via overlying memory cells and to underlying conductors via underlying memory cells.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: A three-dimensional memory array and method for storing data bits and ECC bits therein is provided. A three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is described. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word.

Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.

Abstract: The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A 3-dimensional read only memory includes vertically stacked layers of memory cells. Each of the memory cells includes a mask programmed insulating layer, a pair of diode components, and a pair of crossing-conductors. The conductors (other than those at the top and the bottom of the array) each connect to both overlying conductors via overlying memory cells and to underlying conductors via underlying memory cells.