Patents by Inventor Mark G. Johnson

Mark G. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6525949
    Abstract: A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: February 25, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Joseph G. Nolan, III, Matthew P. Crowley
  • Patent number: 6525953
    Abstract: A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: February 25, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventor: Mark G. Johnson
  • Publication number: 20030026121
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Application
    Filed: September 23, 2002
    Publication date: February 6, 2003
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 6515888
    Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: February 4, 2003
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, P. Michael Farmwald, N. Johan Knall
  • Publication number: 20030018871
    Abstract: The preferred embodiments described herein provide a memory device and methods for use therewith. In one preferred embodiment, a method is presented for using a file system to dynamically respond to variability in an indicated minimum number of memory cells of first and second write-once memory devices. In another preferred embodiment, a method for overwriting data in a memory device is described in which an error code is disregarded after a destructive pattern is written. In yet another preferred embodiment, a method is presented in which, after a block of memory has been allocated for a file to be stored in a memory device, available lines in that block are determined. Another preferred embodiment relates to reserving at least one memory cell in a memory device for file structures or file system structures. A memory device is also provided in which file system structures of at least two file systems are stored in the same memory partition.
    Type: Application
    Filed: September 23, 2002
    Publication date: January 23, 2003
    Inventors: Roger W. March, Christopher S. Moore, Daniel T. Brown, Thomas H. Lee, Mark G. Johnson
  • Patent number: 6483728
    Abstract: A charge pump circuit includes, in a preferred embodiment, a plurality of serially-connected pump stages, each of which is driven by one or more associated clock signals for the stage. The amplitude of the clock signals associated with a respective one of the pump stages differ in amplitude from that of the clock signals associated with at least one other pump stage. As a result, the additional voltage achieved by each successive pump stage may be progressively larger for each successive pump stage. An exemplary charge pump circuit provides clock signals which increase in amplitude with each successive pump stage, and provides with each successive pump stage an output voltage having a magnitude that is a multiplicative factor of the magnitude of the input voltage for the stage. Consequently, the output voltage achieved by the exemplary charge pump circuit is an exponential function of the number of pump stages within the charge pump circuit.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: November 19, 2002
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Joseph G. Nolan, III, Matthew P. Crowley
  • Patent number: 6483736
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: November 19, 2002
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Publication number: 20020083390
    Abstract: The preferred embodiments described herein provide a three-dimensional memory array and method for storing data bits and ECC bits therein. In one preferred embodiment, a three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is provided. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word. Other preferred embodiments are disclosed.
    Type: Application
    Filed: December 22, 2000
    Publication date: June 27, 2002
    Applicant: MATRIX SEMICONDUCTOR, INC.
    Inventors: Thomas H. Lee, James M. Cleeves, Mark G. Johnson
  • Publication number: 20020075719
    Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).
    Type: Application
    Filed: August 13, 2001
    Publication date: June 20, 2002
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, P. Michael Farmwald, N. Johan Knall
  • Patent number: 6385074
    Abstract: An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: May 7, 2002
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Publication number: 20020028541
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: August 13, 2001
    Publication date: March 7, 2002
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner
  • Publication number: 20020027793
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Application
    Filed: August 24, 2001
    Publication date: March 7, 2002
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Patent number: 6351406
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: February 26, 2002
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, P. Michael Farmwald, James M. Cleeves
  • Publication number: 20020018355
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Application
    Filed: August 24, 2001
    Publication date: February 14, 2002
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
  • Publication number: 20010055838
    Abstract: A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.
    Type: Application
    Filed: August 13, 2001
    Publication date: December 27, 2001
    Applicant: Matrix Semiconductor Inc.
    Inventors: Andrew J. Walker, Mark G. Johnson, N. Johan Knall, Igor G. Kouznetsov, Christopher J. Petti
  • Patent number: 6185122
    Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: February 6, 2001
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, P. Michael Farmwald, James M. Cleeves
  • Patent number: 6157244
    Abstract: A temperature sensor is fabricated in an integrated circuit in combination with another device such as a microprocessor using a fabrication technology that is suitable for fabricating the device. Operation of the temperature sensor is based on the bandgap physics of semiconductors using a bandgap reference circuit and an amplifier that generate two measurement voltages, a voltage that is temperature-dependent and a voltage that is temperature-independent. The temperature sensor includes a bandgap power supply circuit that supplies a power supply voltage that is very stable to drive the temperature sensor so that the temperature sensor generates an output signal that is essentially independent of the power supply voltage.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: December 5, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas H. Lee, Mark G. Johnson, John C. Holst
  • Patent number: 6125157
    Abstract: Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: September 26, 2000
    Assignee: Rambus, Inc.
    Inventors: Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson, Benedict C. Lau, Leung Yu, Bruno W. Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Vi Tran, Donald C. Stark
  • Patent number: 6107847
    Abstract: A pulse generating circuit that includes an unbalanced latch and a feedback circuit. The unbalanced latch is configured to generate a latch signal having a predetermined state in response to application of power to the circuit. The feedback circuit is coupled in a negative feedback arrangement with the unbalanced latch and generates a pulse signal for a predetermined period of time in response to the latch signal.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: August 22, 2000
    Assignee: Rambus Inc.
    Inventors: Mark G. Johnson, Kevin S. Donnelly, Clemenz L. Portmann
  • Patent number: 6057739
    Abstract: An electronic system such as a processor or computer system includes a phase-locked loop (PLL) having a PLL parameter modification circuit. In one embodiment, the PLL parameter modification circuit may be programmed to provide one of several current control signals to a charge pump. Additionally, the PLL parameter modification circuit may be programmed to alter a loop filter transfer function by selectively changing resistance and/or capacitance values of the loop filter. Each current control signal modifies the charge pump output control voltage to a VCO differently, and, thus, modifying the current control signals to the charge pump effectively modifies the bandwidth of the PLL. In one embodiment, the PLL parameter modification circuit modifies current control signals to the charge pump by selectively inserting and removing, in accordance with programmable register bit(s) states, diode configured transistors in a current mirror configuration. Thus, a ratio of the output current of the current mirror i.e.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: May 2, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew P. Crowley, Mark G. Johnson