Patents by Inventor Mark H. Somervell

Mark H. Somervell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538684
    Abstract: A processing method is disclosed that enables an improved directed self-assembly (DSA) processing scheme by allowing the formation of improved guide strips in the DSA template that may enable the formation of sub-30 nm features on a substrate. The improved guide strips may be formed by improving the selectivity of wet chemical processing between different organic layers or films. In one embodiment, treating the organic layers with one or more wavelengths of ultraviolet light may improve selectivity. The first wavelength of UV light may be less than 200 nm and the second wavelength of UV light may be greater than 200 mn.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: December 27, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Mark H. Somervell, Ian J. Brown, Ihsan Simms, Ainhoa Negreira, Kathleen Nafus
  • Patent number: 11061332
    Abstract: A patterning method is provided in which a light-sensitive layer is formed, and a target resolution is defined for a pattern to be formed in a target layer. Based on a reference dose and reference LWR that results from a single patterning exposure at an EUV wavelength, the target resolution and reference dose, the light-sensitive layer is subjected to at least two radiation exposures including an EUV patterning exposure at a dose selected to be less than the reference dose and within 15 mJ/cm2-200 mJ/cm2, and a flood exposure at a wavelength of 200 nm-420 nm and a dose of 0.5 J/cm2-20 J/cm2. The light-sensitive layer is then developed to form a mask pattern, which is used to etch the pattern into the target layer with the target resolution and a LWR less than or approximately equal to the reference LWR and ?5 nm.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 13, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Seiji Nagahara
  • Patent number: 10622267
    Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 14, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Ryan L. Burns, Benjamen M. Rathsack, Mark H. Somervell, Makoto Muramatsu
  • Publication number: 20200066509
    Abstract: A processing method is disclosed that enables an improved directed self-assembly (DSA) processing scheme by allowing the formation of improved guide strips in the DSA template that may enable the formation of sub-30 nm features on a substrate. The improved guide strips may be formed by improving the selectivity of wet chemical processing between different organic layers or films. In one embodiment, treating the organic layers with one or more wavelengths of ultraviolet light may improve selectivity. The first wavelength of UV light may be less than 200 nm and the second wavelength of UV light may be greater than 200 mn.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Mark H. Somervell, Ian J. Brown, Ihsan Simms, Ainhoa Negreira, Kathleen Nafus
  • Patent number: 10429745
    Abstract: Methods and systems for PS-CAR photoresist simulation are described. In an embodiment, a method includes determining by simulation at least one process parameter of a lithography process using a radiation-sensitive material. In such an embodiment, the radiation-sensitive material includes: a first light wavelength activation threshold that controls the generation of acid to a first acid concentration in the radiation-sensitive material and controls generation of photosensitizer molecules in the radiation-sensitive material, and a second light wavelength activation threshold that can excite the photosensitizer molecules in the radiation-sensitive material that results in the acid comprising a second acid concentration that is greater than the first acid concentration, the second light wavelength being different from the first light wavelength. In such an embodiment, the method also includes performing a lithography process using the previously-determined at least one process parameter.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 1, 2019
    Assignees: Osaka University, Tokyo Electron Limited
    Inventors: Michael Carcasi, Benjamen M. Rathsack, Mark H. Somervell, Wallace P. Printz, Seiji Nagahara, Seiichi Tagawa
  • Publication number: 20190094698
    Abstract: A patterning method is provided in which a light-sensitive layer is formed, and a target resolution is defined for a pattern to be formed in a target layer. Based on a reference dose and reference LWR that results from a single patterning exposure at an EUV wavelength, the target resolution and reference dose, the light-sensitive layer is subjected to at least two radiation exposures including an EUV patterning exposure at a dose selected to be less than the reference dose and within 15 mJ/cm2-200 mJ/cm2, and a flood exposure at a wavelength of 200 nm-420 nm and a dose of 0.5 J/cm2-20 J/cm2. The light-sensitive layer is then developed to form a mask pattern, which is used to etch the pattern into the target layer with the target resolution and a LWR less than or approximately equal to the reference LWR and ?5 nm.
    Type: Application
    Filed: September 20, 2018
    Publication date: March 28, 2019
    Inventors: Michael A. Carcasi, Mark H. Somervell, Seiji Nagahara
  • Patent number: 10170354
    Abstract: A method for partially filling an open feature on a substrate includes receiving a substrate having a layer with at least one open feature formed therein, wherein the open feature penetrates into the layer from an upper surface and includes sidewalls extending to a bottom of the open feature. The open feature is overfilled with an organic coating that covers the upper surface of the layer and extends to the bottom of the open feature. The method further includes removing a portion of the organic coating to expose the upper surface of the layer and recessing the organic coating to a pre-determined depth from the upper surface to create an organic coating plug of pre-determined thickness at the bottom of the open feature, and converting the chemical composition of the organic coating plug to create an inorganic plug.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 1, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Mark H. Somervell, Benjamen M. Rathsack
  • Publication number: 20180315596
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films (e.g., photoresist on anti-reflective coatings) on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV or UV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located in the film stack. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Steven Scheer, Michael A. Carcasi, Benjamen M. Rathsack, Mark H. Somervell, Joshua S. Hooge
  • Patent number: 10020195
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films (e.g., photoresist on anti-reflective coatings) on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV or UV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located in the film stack. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: July 10, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Steven Scheer, Michael A. Carcasi, Benjamen M. Rathsack, Mark H. Somervell, Joshua S. Hooge
  • Publication number: 20180096905
    Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 5, 2018
    Inventors: Ryan L. Burns, Benjamen M. Rathsack, Mark H. Somervell, Makoto Muramatsu
  • Patent number: 9793137
    Abstract: A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed self-assembly (DSA) pattern overlying the lines, transferring the first pattern to form first line cuts, aligning and preparing a second DSA pattern overlying the lines, and transferring the second pattern to form second line cuts. The DSA patterns include trenches and holes of diameter d, and each comprise a block copolymer having HCP morphology, a characteristic dimension Lo approximately equal to the line pitch, and a minority phase of the diameter d. The trenches are wet by a majority phase of the block copolymer and guide formation of the holes. The aligning and preparation of the DSA patterns include overlapping the two sets of trenches such that areas between holes of one pattern and adjacent holes of the other pattern are shared by adjacent trenches.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 17, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Mark H. Somervell, Benjamen M. Rathsack
  • Patent number: 9746774
    Abstract: A method for mitigating shot noise in extreme ultraviolet (EUV) lithography and patterning of photo-sensitized chemically-amplified resist (PS-CAR) is described. The method includes a first EUV patterned exposure to generate a photosensitizer and a second flood exposure at a wavelength different than the wavelength of the first EUV patterned exposure, to generate acid in regions exposed during the first EUV patterned exposure, wherein the photosensitizer acts to amplify acid generation and improve contrast. The resist may be exposed to heat, liquid solvent, solvent atmosphere, or a vacuum to mitigate the effects of EUV shot noise on photosensitizer concentration which may accrue during the first EUV patterned exposure.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 29, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell
  • Publication number: 20170242342
    Abstract: Methods and systems for PS-CAR photoresist simulation are described. In an embodiment, a method includes determining by simulation at least one process parameter of a lithography process using a radiation-sensitive material. In such an embodiment, the radiation-sensitive material includes: a first light wavelength activation threshold that controls the generation of acid to a first acid concentration in the radiation-sensitive material and controls generation of photosensitizer molecules in the radiation-sensitive material, and a second light wavelength activation threshold that can excite the photosensitizer molecules in the radiation-sensitive material that results in the acid comprising a second acid concentration that is greater than the first acid concentration, the second light wavelength being different from the first light wavelength. In such an embodiment, the method also includes performing a lithography process using the previously-determined at least one process parameter.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Michael Carcasi, Benjamen M. Rathsack, Mark H. Somervell, Wallace P. Printz, Seiji Nagahara, Seiichi Tagawa
  • Patent number: 9715172
    Abstract: A method is provided for forming a patterned topography on a substrate. The substrate is provided with features formed atop that constitute an existing topography, and a template for directed self-assembly (DSA) surrounds the exposed topography. Further to the method, the template is filled with a block copolymer (BCP) to cover the exposed topography, and then the BCP is annealed within the template to drive self-assembly in alignment with the topography. Developing the annealed BCP exposes a DSA pattern immediately overlying the topography.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: July 25, 2017
    Assignee: Tokyo ELectron Limited
    Inventors: Benjamen M. Rathsack, Mark H. Somervell
  • Patent number: 9633847
    Abstract: A method for treating a microelectronic substrate to form a chemical template includes patterning the substrate to form a trench structure with a plurality of trenches of a defined trench width and depositing a photoactive material on the substrate to overfill the trench structure to form a fill portion in the plurality of trenches and an overfill portion above the trench structure. The method further includes exposing the photoactive material to electromagnetic radiation comprising a wavelength that is at least four times greater than the defined trench width such that the overfill portion is modified by the exposure while the electromagnetic radiation fails to penetrate into the plurality of trenches leaving the fill portion unmodified and removing the modified overfill portion of the photoactive material to form a planarized filled trench structure for use as a chemical template for selective reactive ion etching, selective deposition, or directed self-assembly.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 25, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Mark H. Somervell
  • Patent number: 9613801
    Abstract: A method of patterning a layered substrate is provided that includes forming a layer of a block copolymer on a substrate, annealing the layer of the block copolymer to affect microphase segregation such that self-assembled domains are formed, and annealing the layer of the block copolymer a second time to refine or modify the microphase segregation, where one of the annealing steps uses an absorption based heating method.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: April 4, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Benjamen M. Rathsack
  • Publication number: 20160363868
    Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.
    Type: Application
    Filed: July 29, 2016
    Publication date: December 15, 2016
    Inventors: Mark H. SOMERVELL, Benjamen M. RATHSACK, Ian J. BROWN, Steven SCHEER, Joshua S. HOOGE
  • Patent number: 9519227
    Abstract: Methods for measuring photosensitizer concentrations in a photo-sensitized chemically-amplified resist (PS-CAR) patterning process are described. Measured photosensitizer concentrations can be used in feedback and feedforward control of the patterning process and subsequent processing steps. Also described is a metrology target formed using PS-CAR resist, and a substrate including a plurality of such metrology targets to facilitate patterning process control.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 13, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Joshua S. Hooge, Benjamen M. Rathsack, Seiji Nagahara
  • Publication number: 20160358786
    Abstract: Systems and methods for SOC planarization are described. In an embodiment, an apparatus for SOC planarization includes a substrate holder configured to support a microelectronic substrate. Additionally, the apparatus may include a light source configured to emit ultraviolet (UV) light toward a surface of the microelectronic substrate. In an embodiment, the apparatus may also include an isolation window disposed between the light source and the microelectronic substrate. Also, the apparatus may include a gas distribution unit configured to inject gas in a region between the isolation window and the microelectronic substrate. Furthermore, the apparatus may include an etchback leveling component configured to reduce non-uniformity of a UV light treatment of the microelectronic substrate.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 8, 2016
    Inventors: Joshua S. Hooge, Benjamen M. Rathsack, Michael A. Carcasi, Mark H. Somervell, Ian J. Brown, Wallace P. Printz
  • Publication number: 20160343588
    Abstract: A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed self-assembly (DSA) pattern overlying the lines, transferring the first pattern to form first line cuts, aligning and preparing a second DSA pattern overlying the lines, and transferring the second pattern to form second line cuts. The DSA patterns include trenches and holes of diameter d, and each comprise a block copolymer having HCP morphology, a characteristic dimension Lo approximately equal to the line pitch, and a minority phase of the diameter d. The trenches are wet by a majority phase of the block copolymer and guide formation of the holes. The aligning and preparation of the DSA patterns include overlapping the two sets of trenches such that areas between holes of one pattern and adjacent holes of the other pattern are shared by adjacent trenches.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Mark H. Somervell, Benjamen M. Rathsack