Abstract: A method of creating a graded anti-reflective coating (ARC) layer on a thin film is described. The method includes forming the thin film on a substrate, forming an ARC layer on the thin film, and applying a solvent to the ARC layer causing it to swell. A photo-resist layer is formed on the swollen ARC layer. A mixing layer is formed by the diffusion of components from the swollen ARC layer to the photo-resist layer and vice versa. The mixing layer has optical qualities that are distinct from those of either of the ARC layer or the photo-resist layer. The mixing layer forms the graded ARC layer.

Abstract: In a method of removing a film residue from a wafer in a substrate processing system, a surface of the wafer is exposed to a processing liquid to thereby lift a first portion of the film residue off the surface of the wafer. In addition, a continuous or pulsed stream of pressurized gas is applied against the surface of the wafer to remove a second portion of the film residue from the wafer. The method may include rotating the wafer relative to the stream of pressurized gas. The stream of pressurized gas may be applied subsequent to exposing the surface of the wafer to the processing liquid and any residual processing liquid may be removed with the second portion of film residue by the stream of pressurized gas. Alternatively, the stream of pressurized gas may be applied concurrently with the processing liquid to remove the film residue and processing liquid in a single step.

Abstract: A method of creating a graded anti-reflective coating (ARC) layer on a thin film is described. The method includes forming the thin film on a substrate, forming an ARC layer on the thin film, and applying a solvent to the ARC layer causing it to swell. A photo-resist layer is formed on the swollen ARC layer. A mixing layer is formed by the diffusion of components from the swollen ARC layer to the photo-resist layer and vice versa. The mixing layer has optical qualities that are distinct from those of either of the ARC layer or the photo-resist layer. The mixing layer forms the graded ARC layer.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: The invention provides a semiconductive device that comprises interlevel dielectric layers that are located over devices. The interlevel dielectric layers have a dielectric constant (k) less than about 4.0. Interconnects are formed within or over the interlevel dielectric layers. The semiconductive device further comprises an aluminum oxide barrier located between at least one pair of the interlevel dielectric layers. The aluminum oxide barrier is substantially laterally co-extensive with the interlevel dielectric layers.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.