Abstract: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

Abstract: Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.

Abstract: Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

Abstract: A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.

Abstract: A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

Abstract: Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

Abstract: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes.

Abstract: A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: An air particle precipitator and a method of air filtration comprise a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further comprises an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further comprise a metal layer over the carbon nanotube.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: A fin field effect transistor (FinFET) gate comprises a semiconductor wafer; a gate dielectric layer over the semiconductor wafer; a conductive material on the gate dielectric layer; an activated carbon nanotube on a surface of the conductive material; and a plated metal layer on the activated carbon nanotube. Preferably, the carbon nanotube is on a sidewall of the conductive material. The conductive material comprises a first metal layer over the gate dielectric layer, wherein the first metal layer acts as a catalyst for growing the carbon nanotube, wherein the first metal layer is preferably in a range of 1-10 nm in thickness. The semiconductor wafer may comprise a silicon on insulator wafer. The FinFET gate may further comprise a second metal layer disposed between the first metal layer and the gate dielectric layer.

Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.

Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

Abstract: An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.