Patents by Inventor Mark Hakey
Mark Hakey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060228835Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface ; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060226480Abstract: The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Larry Nesbit
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Publication number: 20060220148Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.Type: ApplicationFiled: June 2, 2006Publication date: October 5, 2006Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060205123Abstract: A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.Type: ApplicationFiled: March 10, 2005Publication date: September 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Holmes, Charles Koburger, David Horak, Toshiharu Furukawa, Mark Hakey
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Publication number: 20060202239Abstract: A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the seed layer. The dummy gate defines a location for the gate conductor. Semiconductor devices having a dummy gate plated thereon to a width of between about 10 to about 70 nanometers are also provided.Type: ApplicationFiled: March 10, 2005Publication date: September 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Holmes, Toshiharu Furukawa, Charles Koburger, David Horak, Mark Hakey
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Publication number: 20060195285Abstract: A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. The sacrificial circuit is located in the kerf area or alternatively on each of the plurality of IC chips. A mis-designed IC chip comprises abnormally functioning circuitry.Type: ApplicationFiled: February 25, 2005Publication date: August 31, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pierre Bouchard, Mark Hakey, Mark Masters, Leah Pastel, James Slinkman, David Vallett
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Publication number: 20060172547Abstract: A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.Type: ApplicationFiled: January 28, 2005Publication date: August 3, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060172479Abstract: Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.Type: ApplicationFiled: March 14, 2006Publication date: August 3, 2006Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060169972Abstract: A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor. A method of forming the inventive hybrid semiconductor structure having at least one shared node between the vertical carbon nanotube transistor and the horizontal semiconductor device is also provided.Type: ApplicationFiled: January 31, 2005Publication date: August 3, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, David Horak, Charles Koburger, Mark Masters, Peter Mitchell
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Publication number: 20060172496Abstract: A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.Type: ApplicationFiled: January 28, 2005Publication date: August 3, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell, Larry Nesbit
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Publication number: 20060166432Abstract: A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.Type: ApplicationFiled: January 25, 2005Publication date: July 27, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Holmes, Toshiharu Furukawa, Mark Hakey, David Horak, Charles Koburger, Larry Nesbit
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Publication number: 20060160363Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.Type: ApplicationFiled: January 17, 2005Publication date: July 20, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060154463Abstract: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.Type: ApplicationFiled: January 12, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060128137Abstract: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.Type: ApplicationFiled: December 9, 2004Publication date: June 15, 2006Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell
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Publication number: 20060103818Abstract: A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.Type: ApplicationFiled: November 18, 2004Publication date: May 18, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Holmes, Mark Hakey, Toshiharu Furukawa, David Horak
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Publication number: 20060103830Abstract: An apparatus for holding a wafer and a method for immersion lithography. The apparatus, including a wafer chuck having a central circular vacuum platen, an outer region, and a circular groove centered on the vacuum platen, a top surface of the vacuum platen recessed below a top surface of the outer region and a bottom surface of the groove recessed below the top surface of the vacuum platen; one or more suction ports in the bottom surface of the groove; and a hollow toroidal inflatable and deflatable bladder positioned within the groove.Type: ApplicationFiled: November 18, 2004Publication date: May 18, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Holmes, Toshiharu Furukawa, Mark Hakey, Daniel Corliss, David Horak, Charles Koburger
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Publication number: 20060073394Abstract: A combined wide-image and loop-cutter pattern is provided for both cutting and forming a wide-image section to a hard mask on a substrate formed by sidewall imaging techniques in a reduced number of photolithographic steps. A single mask is formed which provides a wide mask section while additionally providing a mask to protect the critical edges of an underlying hard mask during hard mask etching. After the hard mask is cut into sections, the protective portions of the follow-on mask are removed to expose the critical edges of the underlying hard mask while maintaining shapes necessary for defining wide-image sections. Thus, the hard mask cutting, hard mask critical edge protecting, and large area mask may be formed in a reduced number of steps.Type: ApplicationFiled: October 4, 2004Publication date: April 6, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060073682Abstract: A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.Type: ApplicationFiled: October 4, 2004Publication date: April 6, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060060562Abstract: A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.Type: ApplicationFiled: September 20, 2004Publication date: March 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell, Larry Nesbit, James Slinkman
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Publication number: 20060038167Abstract: A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.Type: ApplicationFiled: August 20, 2004Publication date: February 23, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark Hakey, Mark Masters, Leah Pastel, David Vallett